X95840WV20I-2.7T1 Intersil, X95840WV20I-2.7T1 Datasheet - Page 4

• Manufacturer Part Number: X95840WV20I-2.7T1
• Description: IC XDCP QUAD 256TAP 10K 20-TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X95840WV20I-2.7T1

• Taps: 256
• Resistance (ohms): 10K
• Number Of Circuits: 4
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Operating Specifications
EEPROM SPECS
SERIAL INTERFACE SPECS
V
t
t
t
AA
IN
OL
D
Hysteresis
VccRamp
SYMBOL
(Note 15)
(Note 15)
(Note 15)
(Note 15)
t
t
I
(Note 15)
HD:STA
SU:STA
(Note 15)
LkgDig
t
(Note 15) SCL Falling Edge to SDA
t
I
I
t
Vpor
t
(Note 15) SDA outPut Buffer LOW
Cpin
f
HIGH
LOW
CC1
CC2
I
DCP
V
BUF
V
SCL
SB
IH
IL
V
(Volatile write/read)
V
(nonvolatile write)
V
Leakage Current, at
Pins A0, A1, A2, SDA, SCL,
and WP Pins
DCP Wiper Response Time
Power-on Recall Voltage
V
Power-up Delay
EEPROM Endurance
EEPROM Retention
WP, A2, A1, A0, SDA, and
SCL Input Buffer LOW
Voltage
WP, A2, A1, A0, SDA, and
SCL Input Buffer HIGH
Voltage
SDA and SCL Input Buffer
Hysteresis
Voltage, Sinking 4mA
WP, A2, A1, A0, SDA, and
SCL Pin Capacitance
SCL frEquency
Pulse Width Suppression
Time at SDA and SCL Inputs
Output Data Valid
Time the Bus Must be Free
Before the Start of a New
Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup
Time
START Condition Hold Time From SDA falling edge crossing 30% of V
CC
CC
CC
CC
Supply Current
Supply Current
Current (standby)
Ramp Rate
PARAMETER
4
Over the recommended operating conditions unless otherwise specified.
f
Active, Read and Volatile Write States only)
f
Active, Nonvolatile Write State only)
V
V
Voltage at pin from GND to V
SCL falling edge of last bit of DCP Data Byte to wiper
change
Minimum V
V
completed, and
Temperature
Any pulse narrower than the max spec is suppressed.
SCL falling edge crossing 30% of V
the 30% to 70% of V
SDA crossing 70% of V
SDA crossing 70% of V
condition.
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge. Both crossing
70% of V
falling edge crossing 70% of V
SCL
SCL
CC
CC
CC
= +5.5V,
= +3.6V,
above Vpor, to DCP Initial Value Register recall
= 400kHz; SDA = Open; (for
= 400kHz; SDA = Open; (for
CC
CC
.
≤
I
I
2
2
at which memory recall occurs
75°C
C
C
I
TEST CONDITIONS
2
C
Interface in Standby State
Interface in Standby State
X95840
Interface in standby state
CC
CC
CC
window.
CC
CC
during a STOP condition, to
during the following START
CC
crossing.
crossing.
CC
.
I
I
2
2
CC
C
C
,
,
, until SDA exits
CC
to SCL
0.7*V
150,000
0.05*
1300
1300
V
MIN
-0.3
600
600
600
-10
1.8
0.2
50
CC
0
CC
(Note 1)
TYP
V
0.3*V
CC
MAX
400
900
2.6
0.4
10
10
50
1
3
1
3
5
2
+0.3
CC
July 5, 2006
UNITS
Cycles
Years
V/ms
FN8213.2
kHz
mA
mA
µA
µA
µA
ms
µs
pF
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
V