CS4364-CQZ Cirrus Logic Inc, CS4364-CQZ Datasheet - Page 20

• Manufacturer Part Number: CS4364-CQZ
• Description: IC DAC 103DB 24BIT 6CH 48-LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4364-CQZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 63mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB4364 - EVALUATION BOARD FOR CS4364
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1059

20
4. APPLICATIONS
The CS4364 serially accepts twos complement formatted PCM data at standard audio sample rates including 48,
44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via
the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial
audio interfaces see AN282 “The 2-Channel Serial Audio Interface: A Tutorial”.
The CS4364 can be configured in Hardware Mode by the M0, M1, M2, M3 and M4 pins and in Software Mode
through I²C or SPI.
4.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in
frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and
speed mode is detected automatically during the initialization sequence by counting the number of MCLK
transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are
then set to generate the proper internal clocks.
and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but
MCLK, LRCK and SCLK must be synchronous.
Sample Rate
Sample Rate
Sample Rate
(kHz)
176.4
(kHz)
(kHz)
192
44.1
88.2
32
48
64
96
= Denotes clock ratio and sample rate combinations which are NOT supported under auto
speed-mode detection. Please see
12.2880
11.2896
8.1920
11.2896
12.2880
256x
11.2896
12.2880
8.1920
Table 2. Double-Speed Mode Standard Frequencies
Table 3. Quad-Speed Mode Standard Frequencies
Table 1. Single-Speed Mode Standard Frequencies
128x
64x
12.2880
16.9344
18.4320
384x
16.9344
18.4320
12.2880
16.9344
18.4320
192x
96x
Tables 1
“Switching Characteristics - PCM” on page
16.3840
22.5792
24.5760
512x
Tables 1
MCLK (MHz)
MCLK (MHz)
MCLK (MHz)
16.3840
22.5792
24.5760
22.5792
24.5760
256x
-
128x
3
illustrate several standard audio sample rates
- 3. The LRCK frequency is equal to Fs, the
24.5760
33.8688
36.8640
768x
24.5760
33.8688
36.8640
33.8688
36.8640
384x
192x
32.7680
45.1584
49.1520
1024x
14.
45.1584
49.1520
32.7680
45.1584
49.1520
256x
512x
36.8640
1152x
CS4364
DS619F1