CS4364-CQZ Cirrus Logic Inc, CS4364-CQZ Datasheet - Page 33

• Manufacturer Part Number: CS4364-CQZ
• Description: IC DAC 103DB 24BIT 6CH 48-LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4364-CQZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 63mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB4364 - EVALUATION BOARD FOR CS4364
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1059

DS619F1
6. REGISTER DESCRIPTION
Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted.
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
PART4
CPEN
7
0
7
0
Chip Revision (Address 01h)
Mode Control 1 (Address 02h)
Part Number ID (PART) [Read Only]
01100 - CS4364
Revision ID (REV) [Read Only]
000 - Revision A0
001 - Revision B0
Function:
This read-only register can be used to identify the model and revision number of the device.
Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-
isters and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user
should write this bit within 10 ms following the release of Reset.
Freeze Controls (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously,
enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
FREEZE
PART3
6
1
6
0
DSD/PCM
PART2
5
1
5
0
Reserved
PART1
4
0
4
0
DAC3_DIS
PART0
3
0
3
0
DAC2_DIS
REV2
2
2
0
-
DAC1_DIS
REV1
1
1
0
-
CS4364
REV0
PDN
0
0
1
-
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