CS4364-CQZ Cirrus Logic Inc, CS4364-CQZ Datasheet - Page 36

• Manufacturer Part Number: CS4364-CQZ
• Description: IC DAC 103DB 24BIT 6CH 48-LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4364-CQZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 63mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB4364 - EVALUATION BOARD FOR CS4364
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1059

36
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Direct DSD Conversion (DIR_DSD)
Function:
When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control func-
tions.
When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.
In this mode, the full-scale DSD and PCM levels will not be matched (see
performance may be reduced, the volume control is inactive, and the 50 kHz low-pass filter is not available
(see
Static DSD Detect (STATIC_DSD)
Function:
When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,
sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE
register.
When set to 0, this function is disabled.
Invalid DSD Detect (INVALID_DSD)
Function:
When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-
tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE
register.
When set to 0 (default), this function is disabled.
DSD Phase Modulation Mode Select (DSD_PM_MODE)
Function:
When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for Phase Modulation
Mode. (See
When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for Phase Modulation Mode.
DSD Phase Modulation Mode Enable (DSD_PM_EN)
Function:
When set to 1, DSD Phase Modulation Input Mode is enabled and the DSD_PM_MODE bit should be set
accordingly.
When set to 0 (default), this function is disabled (DSD normal mode).
Section 2
Figure 16 on page
for filter specifications).
24.)
Section
2), the dynamic range
CS4364
DS619F1