CS4364-CQZ Cirrus Logic Inc, CS4364-CQZ Datasheet - Page 34

• Manufacturer Part Number: CS4364-CQZ
• Description: IC DAC 103DB 24BIT 6CH 48-LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4364-CQZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 63mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB4364 - EVALUATION BOARD FOR CS4364
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1059

34
6.2.3
6.2.4
6.2.5
6.3
6.3.1
DIF3
7
0
PCM Control (Address 03h)
PCM/DSD Selection (DSD/PCM)
Default = 0
0 - PCM
1 - DSD
Function:
This function selects DSD or PCM Mode. The appropriate data and clocks should be present before
changing modes, or else MUTE should be selected.
DAC Pair Disable (DACx_DIS)
Default = 0
0 - DAC Pair x Enabled
1 - DAC Pair x Disabled
Function:
When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate
the possibility of audible artifacts.
Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port Mode can occur.
Digital Interface Format (DIF)
Default = 0000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The DSD/PCM bit determines whether
PCM or DSD Mode is selected.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in
Note:
to ensure proper switching from one mode to another.
While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set
DIF2
6
0
DIF1
5
0
DIF0
4
0
Figures
Reserved
3
0
8-15.
Reserved
2
0
FM1
1
1
CS4364
DS619F1
FM0
0
1