HI5741BIB Intersil, HI5741BIB Datasheet - Page 10

• Manufacturer Part Number: HI5741BIB
• Description: IC DAC 14-BIT 100MSPS 28-SOIC
• Manufacturer: Intersil

Specifications of HI5741BIB

• Settling Time: 20ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 650mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Multiplying Capability
The HI5741 can operate in two different multiplying
configurations. For frequencies from DC to 100kHz, a signal
of up to 0.6V
as shown in Figure 22.
The signal must have a DC value such that the peak
negative voltage equals -1.25V. Alternately, a capacitor can
be placed in series with REF OUT if a DC multiplying is not
required. The lower input bandwidth can be calculated using
the following formula:
For multiplying frequencies above 100kHz, the CTRL IN pin
can be driven directly as seen in Figure 23.
The nominal input/output relationship is defined as:
In order to prevent the full scale output current from
exceeding 20.48mA, the R
according to the following equation:
The circuit in Figure 23 can be tuned to adjust the lower
cutoff frequency by adjusting capacitor values. Table 1
illustrates the relationship.
R
FIGURE 22. LOW FREQUENCY MULTIPLYING BANDWIDTH
C
∆I
FIGURE 23. HIGH FREQUENCY MULTIPLYING BANDWIDTH
SET
IN
OUT
=
=
-------------------------------------------
(
=
2
----------------------------------------------------------------------------------------- -
I
π
V
OUT
∆V
------------- -
V
80Ω
IN
) 1400
50Ω
IN
(
CIRCUIT
IN
P-P
(
CIRCUIT
1
Full scale
C
can be applied directly to the REF OUT pin
) f
0.01µF
(
IN
200Ω
C
IN
1
(OPTIONAL)
16V
)
AV
REF
)
EE
–
C
SET
⎛
⎝
2
AV
V
---------------------------- -
10
IN PEAK
EE
80Ω
resistor must be adjusted
(
CTRL OUT
CTRL IN
REF OUT
RSET
CTRL OUT
CTRL IN
)
⎞
⎠
HI5741
HI5741
HI5741
Also, the input signal must be limited to 1V
distortion in the DAC output current caused by excessive
modulation of the internal current sources.
Outputs
The outputs I
outputs. Current is steered to either I
to the digital input code. The sum of the two currents is always
equal to the full scale current minus one LSB. The current
output can be converted to a voltage by using a load resistor.
Both current outputs should have the same load resistor (64Ω
typically). By using a 64Ω load on the output, a 50Ω effective
output resistance (R
parallel resistance seen looking back into the output. This is the
nominal value of the R2R ladder of the DAC. The 50Ω output is
needed for matching the output with a 50Ω line. The load
resistor should be chosen so that the effective output resistance
(R
V
I
14 bits, so it is not recommended that it be used in conjunction
with I
compliance range of the output is from -1.25V to 0V, with a
1V
Settling Time
The settling time of the HI5741 is measured as the time it
takes for the output of the DAC to settle to within a ±defined
error band of its final value during a
0001 0000.... or 1111... to 1110 1111...) scale transition. In
defining settling time specifications for the HI5741, two levels
of accuracy are considered. The accuracy levels defined for
the HI5741 are 12 (or 0.024%) and 13 (0.012%) bits.
Glitch
The output glitch of the HI5741 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically, the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). Unequal delay
paths through the device can also cause one current source
OUT
OUT
INPUT CODE (D13-D0)
OUT
P-P
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0000
OUT
is defined in the reference section. I
= I
) matches the line resistance. The output voltage is:
voltage swing allowed within this range.
100kHz
>1MHz
TABLE 2. INPUT CODING vs CURRENT OUTPUT
f
OUT
IN
in a differential-to-single-ended application. The
OUT
TABLE 1. CAPACITOR SELECTION
x R
OUT
and I
OUT
.
OUT
) is achieved due to the 227Ω (±15%)
0.001µF
0.01µF
are complementary current
I
C
OUT
1
-20.48
-10.24
0
(mA)
OUT
1
/
16
OUT
th (code 0000... to
or I
P-P
OUT
is not trimmed to
September 20, 2006
I
to avoid
OUT
in proportion
0.1µF
-10.24
-20.48
1µF
C
2
0
(mA)
FN4071.12