8406801VA Intersil, 8406801VA Datasheet - Page 4

• Manufacturer Part Number: 8406801VA
• Manufacturer: Intersil

Specifications of 8406801VA

• Operating Temperature (max): 125C
• Operating Temperature (min): -55
• Package Type: CDIP
• Pin Count: 18
• Mounting: Through Hole
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
Oscillator
The oscillator circuit of the 82C84A is designed primarily for
use with an external parallel resonant, fundamental mode
crystal from which the basic operating frequency is derived.
The crystal frequency should be selected at three times the
required CPU clock. X1 and X2 are the two crystal input
crystal connections. For the most stable operation of the
oscillator (OSC) output circuit, two capacitors (C1 = C2) as
shown in the waveform figures are recommended. The
output of the oscillator is buffered and brought out on OSC
so that other system timing signals can be derived from this
stable, crystal-controlled source.
Capacitors C1, C2 are chosen such that their combined
capacitance
matches the load capacitance as specified by the crystal
manufacturer. This ensures operation within the frequency
tolerance specified by the crystal manufacturer.
Clock Generator
The clock generator consists of a synchronous divide-by-
three counter with a special clear input that inhibits the
counting. This clear input (CSYNC) allows the output clock
to be synchronized with an external event (such as another
82C84A clock). It is necessary to synchronize the CSYNC
input to the EFI clock external to the 82C84A. This is
accomplished with two flip-flops. (See Figure 1). The counter
output is a 33% duty cycle clock at one-third the input
frequency.
NOTE: The F/C input is a strapping pin that selects either the crystal
Frequency
Type of Operation
Unwanted Modes
Load Capacitance
PARAMETER
oscillator or the EFI input as the clock for the ÷ 3 counter. If
the EFI input is selected as the clock source, the oscillator
section can be used independently for another clock source.
Output is taken from OSC.
CT =
TABLE 1. CRYSTAL SPECIFICATIONS
--------------------- - (Including stray capacitance)
C1 + C2
C1 x C2
2.4 - 25MHz, Fundamental, “AT” cut
Parallel
6dB (Minimum)
18 - 32pF
4
TYPICAL CRYSTAL SPEC
82C84A
82C84A
Clock Outputs
The CLK output is a 33% duty cycle clock driver designed to
drive the 80C86, 80C88 processors directly. PCLK is a
peripheral clock signal whose output frequency is 1/2 that of
CLK. PCLK has a 50% duty cycle.
Reset Logic
The reset logic provides a Schmitt trigger input (RES) and a
synchronizing flip-flop to generate the reset timing. The reset
signal is synchronized to the falling edge of CLK. A simple RC
network can be used to provide power-on reset by utilizing this
function of the 82C84A.
READY Synchronization
Two READY input (RDY1, RDY2) are provided to
accommodate two system busses. Each input has a qualifier
(AEN1 and AEN2, respectively). The AEN signals validate
their respective RDY signals. If a Multi-Master system is not
being used the AEN pin should be tied LOW.
Synchronization is required for all asynchronous active-going
edges of either RDY input to guarantee that the RDY setup
and hold times are met. Inactive-going edges of RDY in
normally ready systems do not require synchronization but
must satisfy RDY setup and hold as a matter of proper system
design.
The ASYNC input defines two modes of READY
synchronization operation.
When ASYNC is LOW, two stages of synchronization are
provided for active READY input signals. Positive-going
asynchronous READY inputs will first be synchronized to flip-
flop one of the rising edge of CLK (requiring a setup time
tR1VCH) and the synchronized to flip-flop two at the next
falling edge of CLK, after which time the READY output will go
active (HIGH). Negative-going asynchronous READY inputs
will be synchronized directly to flip-flop two at the falling edge
of CLK, after which the READY output will go inactive. This
mode of operation is intended for use by asynchronous
(normally not ready) devices in the system which cannot be
guaranteed by design to meet the required RDY setup timing,
TR1VCL, on each bus cycle.
When ASYNC is high or left open, the first READY flip-flop is
bypassed in the READY synchronization logic. READY inputs
are synchronized by flip-flop two on the falling edge of CLK
before they are presented to the processor. This mode is
available for synchronous devices that can be guaranteed to
meet the required RDY setup time.
ASYNC can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in the
system.
December 6, 2005
FN2974.3