PRIXP425BC 869083

Manufacturer Part NumberPRIXP425BC 869083
ManufacturerIntel
PRIXP425BC 869083 datasheet
 


Specifications of PRIXP425BC 869083

Core Operating Frequency400MHzPackage TypeBGA
Pin Count492MountingSurface Mount
Operating Temperature (max)70COperating Temperature (min)0C
Operating Temperature ClassificationCommercialLead Free Status / Rohs StatusCompliant
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®
Intel
IXP42X Product Line of Network
Processors and IXC1100 Control Plane
Processor
Product Features
For a complete list of product features, see
The following features do
not require enabling
software:
Intel XScale
MHz
PCI Interface
USB v1.1 Device Controller
SDRAM Interface
High-Speed UART
Console UART
Internal Bus Performance Monitoring
Unit
16 GPIOs
Four Internal Timers
Packaging
— 492-pin PBGA
Commercial/Extended Temperature
Typical Applications
High-Performance DSL Modem
High-Performance Cable Modem
Residential Gateway
SME Router
Network Printers
“Product Features” on page
The following features do
require enabling software:
®
Processor — Up to 533
Note:
Datasheet
12.
Encryption/Authentication
(AES,DES,3DES,SHA-1,MD5)
Two High-Speed, Serial Interfaces
Three Network Processor Engines
Up to two MII Interfaces
One UTOPIA Level 2 Interface
Multi-Channel HDLC
®
Refer to the Intel
IXP400 Software
Programmer’s Guide for information on
which features are currently enabled.
Control Plane
Integrated Access Device (IAD)
Set-Top Box
Access Points (802.11a/b/g)
Industrial Controllers
Document Number: 252479-006US
August 2006

PRIXP425BC 869083 Summary of contents

  • Page 1

    ... Two High-Speed, Serial Interfaces Three Network Processor Engines Up to two MII Interfaces One UTOPIA Level 2 Interface Multi-Channel HDLC ® Refer to the Intel IXP400 Software Programmer’s Guide for information on which features are currently enabled. Control Plane Integrated Access Device (IAD) Set-Top Box Access Points (802 ...

  • Page 2

    ... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...

  • Page 3

    ... High-Speed and Console UARTs ............................................................... 25 2.1.11 GPIO .................................................................................................... 25 2.1.12 Internal Bus Performance Monitoring Unit (IBPMU) ..................................... 25 2.1.13 Interrupt Controller ................................................................................ 26 2.1.14 Timers .................................................................................................. 26 2.1.15 AHB Queue Manager............................................................................... 26 ® 2.2 Intel XScale Processor ..................................................................................... 26 2.2.1 Super Pipeline........................................................................................ 27 2.2.2 Branch Target Buffer (BTB)...................................................................... 28 2.2.3 Instruction Memory Management Unit (IMMU)............................................ 29 2 ...

  • Page 4

    ... Power Sequence .............................................................................................. 127 5.7 I and Total Average Power ............................................................................. 128 CC 6.0 Ordering Information............................................................................................. 130 ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 4 ® Intel IXP42X product line and IXC1100 control plane processors Document Number: 252479-006US August 2006 ...

  • Page 5

    ... Intel IXP422 Network Processor Block Diagram .......................................................... 19 ® 4 Intel IXP421 Network Processor Block Diagram .......................................................... 19 ® 5 Intel IXP420 Network Processor Block Diagram .......................................................... 20 ® 6 Intel XScale Technology Block Diagram..................................................................... 27 7 492-Pin Lead PBGA Package ...................................................................................... 49 8 Package Markings .................................................................................................... Power Filtering Diagram................................................................................. 80 CCPLL1 10 V Power Filtering Diagram................................................................................. 81 ...

  • Page 6

    ... Part Numbers for the Intel 22 Ball Map Assignment for the Intel 23 Ball Map Assignment for the Intel 24 Ball Map Assignment for the Intel 25 Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor ................................................................72 26 Operating Conditions ................................................................................................83 27 PCI DC Parameters ...................................................................................................83 28 USB v1 ...

  • Page 7

    ... SDRAM Output Timings Values................................................................................... 96 55 Signal Timing With Respect to Clock Rising Edge .......................................................... 97 ® 56 Intel Multiplexed Mode Values................................................................................ 100 57 Intel Simplex Mode Values ...................................................................................... 103 58 Motorola* Multiplexed Mode Values .......................................................................... 105 59 Motorola* Simplex Mode Values ............................................................................... 107 60 HPI Timing Symbol Description ................................................................................ 111 61 HPI-8 Mode Write Access Values .............................................................................. 111 62 HPI-16 Multiplexed Write Accesses Values ...

  • Page 8

    ... Added footnote to Table 19, “System Interface††” regarding system level reset 8. Added part number for IXP423 on Numbers for the Intel® IXP42X Product Line of Network Processors” 9. Added note 4 to Table 27, “PCI DC Parameters” 10. Changed VIH “Minimum” parameter to 2.0 in “ ...

  • Page 9

    ... Incorporated specification changes, specification clarifications and ® document changes from the Intel IXP42X Product Line of Network Processors Specification Update (252702-001). ® Incorporated information for the Intel Processor. Initial release of this document. Document reissued, without “Confidential” marking. § § ® Intel ...

  • Page 10

    ... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 10 ® Intel IXP42X product line and IXC1100 control plane processors Document Number: 252479-006US August 2006 ...

  • Page 11

    ... Detailed functional descriptions — other than parametric performance — are published in the Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer’ ...

  • Page 12

    ... This section outlines the features that apply to the Intel Network Processors and IXC1100 Control Plane Processor Some of the features described in this document require enablement by software delivered by Intel. Some features may not be enabled with current software releases. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ...

  • Page 13

    ... Intel IXP42X product line and IXC1100 control plane processors The features that require software are identified below. Please refer to the Intel IXP400 Software Programmer’s Guide for information on which features are enabled at this time . ® • Intel XScale — High-performance processor based on Intel XScale — ...

  • Page 14

    ... Support for 8 MB, minimum 256 MB maximum • Expansion interface — 24-bit address — 16-bit data — Eight programmable chip selects — Supports Intel/Motorola* microprocessors • Multiplexed-style bus cycles • Simplex-style bus cycles • DSP support for: — Texas Instruments* DSPs supporting HPI-8 bus cycles • ...

  • Page 15

    ... Supports speeds up to 8.192 MHz — Supports connection to T1/E1 framers — Supports connection to CODEC/SLICs — Eight HDLC Channels Note: This feature requires Intel supplied software. To determine if this feature is enabled by a particular software release, see the Intel 1.2.2 Processor Features Table 3 on page 15 of Network Processors and IXC1100 Control Plane Processor ...

  • Page 16

    ... Commercial X Temperature Extended X Temperature Notes: 1. The features marked “Yes” require enabling software. Please refer to the Intel determine if the feature is enabled. 2. Only the 266 MHz version of the Intel 2.0 Functional Overview ® The Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor are compliant with the ARM ® ...

  • Page 17

    ... North AHB SHA-1/MD5, Arbiter DES/3DES, AES North/South South AHB AHB Bridge AHB/APB 133.32 MHz x 32 bits South Advance High-Performance Bus Bridge PMU Intel XScale fi Processor (AHB) 266/400/533 MHz 32 KB Data Cache Test Logic 32 KB Instruction Cache Unit 2 KB Mini-Data Cache ® ...

  • Page 18

    ... North AHB Ethernet MAC Arbiter North/South South AHB AHB Bridge Arbiter AHB/APB 133.32 MHz x 32 bits South Advance High-Performance Bus Bridge PMU Intel XScale fi Processor (AHB) 266/533 MHz 32 KB Data Cache Test Logic 32 KB Instruction Cache Unit 2 KB Mini-Data Cache Queue ...

  • Page 19

    ... North AHB Ethernet MAC Arbiter North/South South AHB AHB Bridge Arbiter AHB/APB 133.32 MHz x 32 bits South Advance High-Performance Bus Bridge PMU Intel XScale fi fi Core Intel XScale Processor (AHB) 266 MHz 32 KB Data Cache Test Logic 32 KB Instruction Cache ...

  • Page 20

    ... Functional Units The following sections briefly the functional units and their interaction in the system. For more detailed information, refer to the Intel Processors and IXC1100 Control Plane Processor Developer’s Manual. Unless otherwise specified, the functional descriptions apply to all processors in the IXP42X product line and IXC1100 control plane processors ...

  • Page 21

    ... These coprocessors are implemented in hardware, enabling the coprocessors and the NPE processor core to operate in parallel. The combined forces of the hardware multi-threading, local-code store, independent instruction memory, independent data memory, and parallel processing allows the Intel ® XScale processor to be utilized for application purposes. The multi-processing ...

  • Page 22

    ... South AHB The South AHB is a 133.32 MHz, 32-bit bus that can be mastered by the Intel XScale processor, PCI controller, and the AHB/AHB bridge. The targets of the South AHB Bus can be the SDRAM, PCI interface, queue manager, expansion bus, or the APB/AHB bridge ...

  • Page 23

    ... ATM cells, CRC checking/generation, and transfer of data to/from memory. This allows parallel processing of data traffic on the UTOPIA Level 2 interface, off-loading processor overhead required by the Intel XScale processor. The IXP42X product line and IXC1100 control plane processors are compliant with the ATM Forum, UTOPIA Level-2 Specification, Revision 1 ...

  • Page 24

    ... PCI Local Bus Specification, Rev. 2.2. The PCI interface is 32-bit compatible bus and capable of operating as either a host or an option (i.e., not the Host) For more information on PCI Controller support and configuration see the Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer’ ...

  • Page 25

    ... External pull-up/ pull-down resistors are used to tie the signals to particular logic levels. For additional details, refer to Section 8 (Expansion Bus Controller) of the Intel of Network Processors and IXC1100 Control Plane Processor Developer’s Manual.) 2 ...

  • Page 26

    ... The AQM interfaces include an Advanced High-performance Bus (AHB) interface to the NPEs and Intel XScale an event bus (to the NPE condition select logic) and two interrupts to the Intel XScale processor. The AHB interface is used for configuration of the AQM and provides access to queues, queue status and SRAM. Individual queue status for queues 0-31 is communicated to the NPEs via the flag bus ...

  • Page 27

    ... Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc. This PMU is for the Intel XScale monitoring of internal bus performance. • JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for flow-change messages) to debug programs ® ...

  • Page 28

    ... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 28 ® Intel IXP42X product line and IXC1100 control plane processors • Weakly taken • Weakly not taken • Strongly not taken August 2006 ...

  • Page 29

    ... ITLB. Access permissions for each memory domains can be programmed. When an instruction pre-fetch is attempted to an area of memory in violation of access permissions, the attempt is aborted and a pre-fetch abort is sent to the Intel XScale processor for exception processing. The IMMU and DMMU can be enabled or disabled together. ...

  • Page 30

    ... The D-cache (and mini-data cache) work with the load buffer and pend buffer to provide “hit-under-miss” capability that allows the Intel XScale other data in the cache after a “miss” is encountered. The D-cache (and mini-data cache) works in conjunction with the write buffer for data that stored to memory ...

  • Page 31

    ... D-cache, mini-data cache, or memory using two STC or LDC instructions. The signed multiply-accumulates (MIAxy) multiply either the high/high, low/ low, high/low, or low/high 16 bits of a 32-bit Intel XScale (multiplier) and another 32-bit Intel XScale to produce a full, 32-bit product that is sign-extended to 40 bits and added to the 40- bit accumulator ...

  • Page 32

    ... Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint, external debug breakpoint, exception vector trap, and trace buffer full breakpoint. Once execution has stopped, the debugger application code can examine or modify the Intel ® XScale processor’s state, coprocessor state, or memory. The debugger application code can then restart program execution. The debug unit has two hardware-instruction, break point registers ...

  • Page 33

    ... Table 17, “GPIO Interface” on page 46 Table 18, “JTAG Interface” on page 46 Table 19, “System Interface††” on page 47 Table 20, “Power Interface” on page 48 August 2006 Document Number: 252479-006US Table 3 on page Description Reference ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 15. Datasheet 33 ...

  • Page 34

    ... SDM_CS_N[1:0] SDM_WE_N † For a legend of the Type codes, see ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 34 ® Intel IXP42X product line and IXC1100 control plane processors Power Reset Post † Type or Sys Reset Reset SDRAM Address: A0-A12 signals are output during the READ/ ...

  • Page 35

    ... SDRAM and driven low to de-activate the CLK to an external SDRAM. SDRAM Data bus mask: DQM is used to byte select data during read/write access to an external SDRAM. Table 5 on page ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Description 33. Datasheet 35 ...

  • Page 36

    ... No change is required to existing designs that have this signal pulled low. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 36 ® Intel IXP42X product line and IXC1100 control plane processors Post † Type Reset PCI Address/Data bus used to transfer address and bidirectional data to and from multiple PCI devices ...

  • Page 37

    ... The PCI clock rate can operate MHz. Should be pulled high utilized in the system. Table 5 on page 33. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Description †† with a 10-KΩ resistor when not being Datasheet 37 ...

  • Page 38

    ... For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system. No change is required to existing designs that have this signal pulled low. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 38 ® Intel IXP42X product line and IXC1100 control plane processors Power Reset Post † Type or Sys ...

  • Page 39

    ... Z Z I/O Configured as an input upon reset. Should be pulled high being utilized in the system. Table 5 on page ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Description †† with a 10-KΩ resistor when not . CCP †† ...

  • Page 40

    ... Management data clock. Management data interface clock is used to clock the MDIO signal as an output and sample the MDIO as an input. The ETH_MDC is an input on power and can be configured output through an Intel API as documented in the Intel Programmer’s Guide. Table 5 on page 33. Description † ...

  • Page 41

    ... ETH_RXCLK1. Should be pulled high being utilized in the system. Table 5 on page 33. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Description †† through a 10-KΩ resistor when not †† through a 10-KΩ resistor when not † ...

  • Page 42

    ... For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system. No change is required to existing designs that have this signal pulled low. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 42 ® Intel IXP42X product line and IXC1100 control plane processors Power Reset Post † Type or Sys ...

  • Page 43

    ... UTP_IP_ADDR and bringing UTP_OP_FCO to logic 1 during the current clock, followed by the UTP_OP_FCO going to a logic 0 on the next clock cycle. Table 5 on page 33. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Description †† through a 10-KΩ resistor when †† ...

  • Page 44

    ... signal affects accesses that use EX_CS_N[7:0] when the chip select is configured in Intel- or Motorola-mode of operation. Should be pulled high through a 10-KΩ resistor when not being utilized in the system. HPI interface ready signals. Can be configured to be active high or active low. These signals are used to halt accesses using Chip Selects 7 through 4 when the chip selects are configured to operate in HPI mode ...

  • Page 45

    ... Z I/O Negative signal of the differential USB receiver/driver. Table 5 on page 33. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Description †† through a 10-KΩ resistor when not being †† through a 10-KΩ resistor when not being ...

  • Page 46

    ... For a legend of the Type codes, see ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 46 ® Intel IXP42X product line and IXC1100 control plane processors Post † Type Reset VI I 33.33 MHz, sinusoidal input signal. Can be driven by an oscillator. ...

  • Page 47

    ... For a legend of the Type codes, see †† IMPORTANT NOTE: When a system-level reset is asserted to the Intel Network Processors and IXC1100 Control Plane Processor — either via a power-on reset, a system reset Watchdog-Timer reset — and any interface active transaction (particularly the PCI bus or expansion bus, but not precluding any interface), an illegal protocol is generated ...

  • Page 48

    ... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 48 ® Intel IXP42X product line and IXC1100 control plane processors † Description 1.3-V power supply input pins used for the internal logic. 3.3-V power supply input pins used for the peripheral (I/O) logic. ...

  • Page 49

    ... IXP42X product line and IXC1100 control plane processors 4.0 Package and Pinout Information ® The Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor have a 492-ball, plastic ball grid array (PBGA) package for commercial- temperature applications and a pin-for-pin, compatible 492-ball, plastic ball grid array with a drop-in heat spreader (H) for extended-temperature applications ...

  • Page 50

    ... Figure 8. Package Markings Pin #1 (Not a mark) BSMC marking zone: 0.380” max. Note: See Table 21 for specific on “Level 1 Name.” Table 21. Part Numbers for the Intel (Sheet Device ® Intel IXP425 ® Intel IXP425 ® Intel IXP425 ® Intel IXP425 ® ...

  • Page 51

    ... Intel IXP423 Network Processor ® Intel IXP422 Network Processor ® Intel IXP421 Network Processor ® Intel IXP420 Network Processor ® and Intel IXC1100 Control Plane Processor Table 22. Ball Map Assignment for the Intel Ball Signal A1 PCI_AD[27] A2 PCI_GNT_N[1] A3 PCI_GNT_N[3] A4 SDM_DATA[19] A5 SDM_DATA[27] A6 SDM_DATA[26] A7 ...

  • Page 52

    ... Table 22. Ball Map Assignment for the Intel Ball Signal A19 SDM_ADDR[12] A20 SDM_ADDR[9] A21 SDM_ADDR[8] A22 SDM_ADDR[5] A23 EX_RD_N A24 EX_ADDR[1] A25 EX_ADDR[3] A26 EX_ADDR[5] E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] E11 VCCP E12 SDM_DATA[3] E13 ...

  • Page 53

    ... Intel IXP42X product line and IXC1100 control plane processors Table 22. Ball Map Assignment for the Intel Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] J23 VCC J24 EX_ADDR[23] J25 EX_CS_N[2] J26 EX_CS_N[4] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 54

    ... Table 22. Ball Map Assignment for the Intel Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N22 VCC N23 VSS N24 VCC N25 EX_DATA[4] N26 EX_DATA[5] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 55

    ... Intel IXP42X product line and IXC1100 control plane processors Table 22. Ball Map Assignment for the Intel Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 HSS_TXDATA0 U6 VCC U21 VCC U22 GPIO[14] U23 EX_RDY_N[1] U24 EX_RDY_N[2] U25 GPIO[15] U26 EX_DATA[15] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 56

    ... Table 22. Ball Map Assignment for the Intel Ball Signal AA1 HSS_RXDATA0 AA2 VCCP AA3 VSS AA4 HSS_RXCLK1 AA5 ETH_TXDATA0[2] AA6 VCC AA7 ETH_RXDATA0[1] AA8 VSS AA9 ETH_TXDATA1[1] AA10 VCC AA17 VCC AA18 UTP_IP_FCI AA19 UTP_IP_ADDR[0] AA20 VSS AA21 VCC AA22 TXDATA1 ...

  • Page 57

    ... Intel IXP42X product line and IXC1100 control plane processors Table 22. Ball Map Assignment for the Intel Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 ETH_TXEN1 AE5 VCCP AE6 ETH_RXDV1 AE7 VSS AE8 ETH_COL1 AE9 VCCP AE10 VCCPLL1 AE11 VSS ...

  • Page 58

    ... Table 23. Ball Map Assignment for the Intel Ball Signal A1 PCI_AD[27] A2 PCI_GNT_N[1] A3 PCI_GNT_N[3] A4 SDM_DATA[19] A5 SDM_DATA[27] A6 SDM_DATA[26] A7 SDM_DATA[25] A8 SDM_DATA[23] A9 SDM_DATA[14] A10 SDM_DATA[13] A11 SDM_DATA[11] A12 SDM_DATA[10] A13 SDM_DATA[6] A14 SDM_DATA[8] A15 SDM_DQM[1] A16 SDM_CS_N[0] A17 SDM_CLKOUT A18 SDM_RAS_N A19 SDM_ADDR[12] A20 SDM_ADDR[9] A21 ...

  • Page 59

    ... Intel IXP42X product line and IXC1100 control plane processors Table 23. Ball Map Assignment for the Intel Ball Signal E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] E11 VCCP E12 SDM_DATA[3] E13 VSS E14 SDM_DQM[0] E15 VCCP E16 ...

  • Page 60

    ... Table 23. Ball Map Assignment for the Intel Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] J23 VCC J24 EX_ADDR[23] J25 EX_CS_N[2] J26 EX_CS_N[4] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 61

    ... Intel IXP42X product line and IXC1100 control plane processors Table 23. Ball Map Assignment for the Intel Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N22 VCC N23 VSS N24 ...

  • Page 62

    ... Table 23. Ball Map Assignment for the Intel Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 N/C U6 VCC U21 VCC U22 GPIO[14] U23 EX_RDY_N[1] U24 EX_RDY_N[2] U25 GPIO[15] U26 EX_DATA[15] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 63

    ... Intel IXP42X product line and IXC1100 control plane processors Table 23. Ball Map Assignment for the Intel Ball Signal AA1 N/C AA2 VCCP AA3 VSS AA4 N/C AA5 ETH_TXDATA0[2] AA6 VCC AA7 ETH_RXDATA0[1] AA8 VSS AA9 ETH_TXDATA1[1] AA10 VCC AA17 VCC ...

  • Page 64

    ... Table 23. Ball Map Assignment for the Intel Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 ETH_TXEN1 AE5 VCCP AE6 ETH_RXDV1 AE7 VSS AE8 ETH_COL1 AE9 VCCP AE10 VCCPLL1 AE11 VSS AE12 VCCPLL2 AE13 VCCP AE14 N/C AE15 VSS AE16 N/C ...

  • Page 65

    ... Intel IXP42X product line and IXC1100 control plane processors Table 24. Ball Map Assignment for the Intel Ball Signal A1 PCI_AD[27] A2 PCI_GNT_N[1] A3 PCI_GNT_N[3] A4 SDM_DATA[19] A5 SDM_DATA[27] A6 SDM_DATA[26] A7 SDM_DATA[25] A8 SDM_DATA[23] A9 SDM_DATA[14] A10 SDM_DATA[13] A11 SDM_DATA[11] A12 SDM_DATA[10] A13 SDM_DATA[6] A14 SDM_DATA[8] A15 SDM_DQM[1] A16 ...

  • Page 66

    ... Table 24. Ball Map Assignment for the Intel Ball Signal E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] E11 VCCP E12 SDM_DATA[3] E13 VSS E14 SDM_DQM[0] E15 VCCP E16 SDM_BA[0] E17 VSS E18 SDM_ADDR[7] E19 VCCP E20 SDM_ADDR[3] E21 ...

  • Page 67

    ... Intel IXP42X product line and IXC1100 control plane processors Table 24. Ball Map Assignment for the Intel Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] J23 VCC J24 EX_ADDR[23] J25 EX_CS_N[2] J26 EX_CS_N[4] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 68

    ... Table 24. Ball Map Assignment for the Intel Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N22 VCC N23 VSS N24 VCC N25 EX_DATA[4] N26 EX_DATA[5] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 69

    ... Intel IXP42X product line and IXC1100 control plane processors Table 24. Ball Map Assignment for the Intel Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 HSS_TXDATA0 U6 VCC U21 VCC U22 GPIO[14] U23 EX_RDY_N[1] U24 EX_RDY_N[2] U25 GPIO[15] U26 EX_DATA[15] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 70

    ... Table 24. Ball Map Assignment for the Intel Ball Signal AA1 HSS_RXDATA0 AA2 VCCP AA3 VSS AA4 HSS_RXCLK1 AA5 ETH_TXDATA0[2] AA6 VCC AA7 ETH_RXDATA0[1] AA8 VSS AA9 N/C AA10 VCC AA17 VCC AA18 UTP_IP_FCI AA19 UTP_IP_ADDR[0] AA20 VSS AA21 VCC AA22 TXDATA1 ...

  • Page 71

    ... Intel IXP42X product line and IXC1100 control plane processors Table 24. Ball Map Assignment for the Intel Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 N/C AE5 VCCP AE6 N/C AE7 VSS AE8 N/C AE9 VCCP AE10 VCCPLL1 AE11 VSS ...

  • Page 72

    ... Table 25. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal A1 PCI_AD[27] A2 PCI_GNT_N[1] A3 PCI_GNT_N[3] A4 SDM_DATA[19] A5 SDM_DATA[27] A6 SDM_DATA[26] A7 SDM_DATA[25] A8 SDM_DATA[23] A9 SDM_DATA[14] A10 SDM_DATA[13] A11 SDM_DATA[11] A12 SDM_DATA[10] A13 SDM_DATA[6] A14 SDM_DATA[8] A15 SDM_DQM[1] A16 SDM_CS_N[0] A17 ...

  • Page 73

    ... Intel IXP42X product line and IXC1100 control plane processors Table 25. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] E11 VCCP E12 ...

  • Page 74

    ... Table 25. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] J23 VCC J24 EX_ADDR[23] J25 EX_CS_N[2] J26 EX_CS_N[4] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 75

    ... Intel IXP42X product line and IXC1100 control plane processors Table 25. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS N14 VSS N15 ...

  • Page 76

    ... Table 25. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 N/C U6 VCC U21 VCC U22 GPIO[14] U23 EX_RDY_N[1] U24 EX_RDY_N[2] U25 GPIO[15] U26 EX_DATA[15] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 77

    ... Intel IXP42X product line and IXC1100 control plane processors Table 25. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal AA1 N/C AA2 VCCP AA3 VSS AA4 N/C AA5 ETH_TXDATA0[2] AA6 VCC AA7 ETH_RXDATA0[1] ...

  • Page 78

    ... Table 25. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 ETH_TXEN1 AE5 VCCP AE6 ETH_RXDV1 AE7 VSS AE8 ETH_COL1 AE9 VCCP AE10 VCCPLL1 AE11 VSS AE12 VCCPLL2 ...

  • Page 79

    ... Electrical Specifications 5.1 Absolute Maximum Ratings Parameter Ambient Air Temperature (Extended) Ambient Air Temperature (Commercial) Supply Voltage (Intel XScale Supply Voltage I/O Supply Voltage Oscillator (V Supply Voltage Oscillator (V Supply Voltage PLL (V Supply Voltage PLL (V Voltage On Any I/O Ball Storage Temperature Warning: Stressing the device beyond the “ ...

  • Page 80

    ... CCPLL1 CCPLL2 To reduce voltage-supply noise on the analog sections of the Intel Line of Network Processors and IXC1100 Control Plane Processor, the phase-lock loop circuits (V , CCPLL1 voltage supplies. The filter circuits for each supply are shown in the following sections. 5.2.1 V Requirement CCPLL1 A parallel combination of a 10-nF capacitor — for bypass — and a 200-nF capacitor — ...

  • Page 81

    ... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ® Intel IXP42X Product Line / ® Intel IXC1100 Control Plane V SS Processor B1681-03 pin and V CCP_OSC SSP_OSC ® Intel IXP42X Product Line / ® Intel IXC1100 Control Plane Processor B1675-04 Datasheet 81 ...

  • Page 82

    ... V SS RCOMP ® Intel 34 Ω, ® Intel IXC1100 Control Plane + supply pin. Both SSOSC pin and the CCOSC ® Intel IXP42X Product Line / ® Intel IXC1100 Control Plane Processor B1676-03 IXP42X Product Line / Processor B1672-02 August 2006 Document Number: 252479-006US ...

  • Page 83

    ... V -10 IN CCP Conditions Min. 2 OUT 2.8 -6 IOUT = 6 < V < V -10 IN CCP ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Typ. Max. Units Notes 3.3 3.465 V 1.3 1.365 V 1.3 1.365 V 3.3 3.465 V 1.3 1.365 V 1.3 1.365 V Typ. ...

  • Page 84

    ... OL Note: 1. These values are typical values seen by the manufacturing process and are not tested. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 84 ® Intel IXP42X product line and IXC1100 control plane processors Conditions OUT OUT V > 2.4 V ...

  • Page 85

    ... IH (MAX) CCP = -2 V for a pulse width < cannot be exceeded. IL (MIN) Conditions Min. 2 2.4 OUT I = 4mA OUT 0 < V < V -10 IN CCP ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Typ. Max. Units Notes 10 µ Typ. Max. Units Notes V 1 0.8 ...

  • Page 86

    ... Note: 1. These values are typical values seen by the manufacturing process and are not tested. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 86 ® Intel IXP42X product line and IXC1100 control plane processors Conditions Min. Typ. 2 2.4 ...

  • Page 87

    ... Min. 2 2.4 OUT OUT 0 < V < V -10 IN CCP Conditions Min. 1.0 0 < V < IN -500 1.3V ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Min. Typ. Max. Units 2.0 V 0.8 V 2.4 V 0.4 V 2.4 V 0.4 V -10 10 µA CCP 5 pF Typ ...

  • Page 88

    ... Please refer to the application note titled Spread Spectrum Clocking to Reduce EMI Application Note, when designing a product that utilizes spread spectrum clocking. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 88 ® Intel IXP42X product line and IXC1100 control plane processors Conditions Min. Typ. 2.0 (Oscillator Reference) Parameter Min ...

  • Page 89

    ... IXP42X Product Line / ® Intel IXC1100 Control Plane Processor OSC_IN Oscillator OSC_OUT 33 MHz Parameter Min. Max Parameter Min. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor B1678-03 66 MHz Units Notes Min. Max 1.5 4 V/ns Nom. Max. Units ...

  • Page 90

    ... The AC timing waveforms are shown in the following sections. 5.5.2.1 PCI Figure 15. PCI Output Timing CLK Output Delay ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 90 ® Intel IXP42X product line and IXC1100 control plane processors Parameter Min. 35 Parameter Min. 40 Parameter Min. 15. clk2out(b) Nom ...

  • Page 91

    ... For additional information, see the PCI Local Bus Specification, Rev. 2.2. August 2006 Document Number: 252479-006US and V = 0.2 V LOW CC T setup(b) Inputs 33 MHz Parameter Min. Max 10 ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T hold Valid A9573-01 66 MHz Units Min. Max ...

  • Page 92

    ... UTP_IP_FCI, and UTP_OP_FCI. Figure 18. UTOPIA Level 2 Output Timings Clock Signals ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 92 ® Intel IXP42X product line and IXC1100 control plane processors Tsetup Thold Parameter Min Tclk2out Tholdout A9578-01 Max. ...

  • Page 93

    ... ETH_TXDATA and ETH_TXEN hold time after T 2 ETH_TXCLK. Note: 1. These values satisfy the MII specification requirement clock to output delay. August 2006 Document Number: 252479-006US Parameter T 1 Parameter ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Min. Max. Units Notes A9580-01 Min ...

  • Page 94

    ... MDIO Figure 21. MDIO Output Timings ETH_MDC ETH_MDIO Note: NPE is sourcing MDIO. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 94 ® Intel IXP42X product line and IXC1100 control plane processors T 3 Parameter Min. 5 A9581-01 Max. Units ...

  • Page 95

    ... Input hold time after the rising edge of the clock. T Inputs included in this timing are SDM_DQ[31:0] hold (during a read operation). August 2006 Document Number: 252479-006US Parameter T setup Parameter ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T 4 A9583-02 Min. Max. Units Notes ETH_MDC ...

  • Page 96

    ... Note: 1. Timing test were performed with a 70-pF load to ground. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 96 ® Intel IXP42X product line and IXC1100 control plane processors Data Valid T clk2out T holdout Parameter Min. 1.5 A9584-01 Max. ...

  • Page 97

    ... Control signal and data output valid after clock rising edge Input Setup time with respect to clock rising edge. Input Hold time with respect to clock rising edge. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 T5 1-4 Cycles ...

  • Page 98

    ... EX_ADDR[23:0] EX_ALE EX_IOWAIT_N EX_RD_N EX_DATA[15:0] Valid Address ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 98 ® Intel IXP42X product line and IXC1100 control plane processors 1-4 Cycles 1-16 Cycles T ale2valcs Valid Address T rdsetup Valid Data ...

  • Page 99

    ... August 2006 Document Number: 252479-006US 2-5 Cycles 1-4 Cycles 1-16 Cycles T ale2valcs Valid Address T wrpulse T dval2valwrt T ale2addrhold Valid Address Valid Data ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 T5 1-4 Cycles 1-16 Cycles T recov T dhold2afterwr B3748-001 Datasheet 99 ...

  • Page 100

    ... Timing tests were performed with a 70-pF capacitor to ground. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 100 ® Intel IXP42X product line and IXC1100 control plane processors Parameter Document Number: 252479-006US Min. Max. Units Notes 1 ...

  • Page 101

    ... EX_IOWAIT_N EX_RD_N EX_DATA[15:0] August 2006 Document Number: 252479-006US 1-4 Cycles 1-4 Cycles 1-16 Cycles Valid Address T rdsetup Valid Data ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 T5 1-4 Cycles 1-16 Cycles T recov T rdhold B3749-002 Datasheet 101 ...

  • Page 102

    ... EX_CLK EX_CS_N[0] EX_ADDR[23:0] EX_IOWAIT_N EX_WR_N EX_DATA[15:0] ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 102 ® Intel IXP42X product line and IXC1100 control plane processors 1-4 Cycles 1-4 Cycles 1-16 Cycles 1-4 Cycles Valid Address T T wrpulse ...

  • Page 103

    ... Intel IXP42X product line and IXC1100 control plane processors Table 57. Intel Simplex Mode Values Symbol Parameter T Valid address to valid chip select addr2valcs T Write data valid prior to EX_WR_N falling edge dval2valwrt T Pulse width of the EX_WR_N wrpulse T Valid data after the rising edge of EX_WR_N ...

  • Page 104

    ... EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0] Valid Address ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 104 ® Intel IXP42X product line and IXC1100 control plane processors 2-5 Cycles 1-4 Cycles 1-16 Cycles T ale2valcs Valid Address T rdsetup ...

  • Page 105

    ... Cycles 1-4 Cycles 1-16 Cycles T ale2valcs Valid Address T dspulse T dval2valds T ale2addrhold Valid Address Valid Data ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 T5 1-4 Cycles 1-16 Cycles T recov B3752-001 Min. Max. Units Notes 1 4 Cycles ...

  • Page 106

    ... EX_IOWAIT_N EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0] ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 106 ® Intel IXP42X product line and IXC1100 control plane processors 1-4 Cycles 1-4 Cycles 1-16 Cycles 1-4 Cycles T ad2valcs Valid Address ...

  • Page 107

    ... Document Number: 252479-006US 1-4 Cycles 1-4 Cycles 1-16 Cycles T ad2valcs Valid Address T dspulse T dval2valds Valid Data Parameter ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 T5 1-4 Cycles 1-16 Cycles T recov T dhold2afterds B3754-001 Min. Max. Units Notes 1 4 ...

  • Page 108

    ... Timing tests were performed with a 70-pF capacitor to ground. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 108 ® Intel IXP42X product line and IXC1100 control plane processors Parameter Document Number: 252479-006US Min. Max. Units Notes 15 ...

  • Page 109

    ... Intel IXP42X product line and IXC1100 control plane processors Figure 34. HPI-8 Mode Read Accesses August 2006 Document Number: 252479-006US ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 109 ...

  • Page 110

    ... Figure 35. HPI-8 Mode Write Accesses ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 110 ® Intel IXP42X product line and IXC1100 control plane processors Document Number: 252479-006US August 2006 ...

  • Page 111

    ... The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel IXP42X Product Line and Intel recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de- active ...

  • Page 112

    ... The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel IXP42X Product Line and Intel recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de- active ...

  • Page 113

    ... Intel IXP42X product line and IXC1100 control plane processors Figure 36. HPI-16 Multiplexed Write Mode August 2006 Document Number: 252479-006US ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 113 ...

  • Page 114

    ... The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel IXP42X Product Line and Intel recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de- active ...

  • Page 115

    ... Intel IXP42X product line and IXC1100 control plane processors Figure 37. HPI-16 Multiplex Read Mode August 2006 Document Number: 252479-006US ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 115 ...

  • Page 116

    ... The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel IXP42X Product Line and Intel recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de- active ...

  • Page 117

    ... Intel IXP42X product line and IXC1100 control plane processors Figure 38. HPI-16 Simplex Read Mode August 2006 Document Number: 252479-006US ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 117 ...

  • Page 118

    ... The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel IXP42X Product Line and Intel the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-active. ...

  • Page 119

    ... Intel IXP42X product line and IXC1100 control plane processors Figure 39. HPI-16 Simplex Write Mode August 2006 Document Number: 252479-006US ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 119 ...

  • Page 120

    ... EX_DATA[15:0] Note: Notice that the access is an Intel-style simplex read access. The data strobe phase is set to a value to last three clock cycles. The data is returned from the peripheral device prior to the three clocks and the peripheral device de-asserts EX_IOWAIT_N. The data strobe phase terminates after two clocks even though the strobe phase was configured to pulse for three clocks. ® ...

  • Page 121

    ... EX_CS_ N[0] EX_ADDR[ EX_ IOWAIT_N EX_RD_N EX_DATA[15:0] August 2006 Document Number: 252479-006US T1=3 h T2 Cycles 4 Cycles 16 Cycles .... Valid Address Valid Data ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 Cycles 16 Cycles ... . 2 Cycles B5243- 01 Datasheet 121 ...

  • Page 122

    ... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 122 ® Intel IXP42X product line and IXC1100 control plane processors Valid Data Valid Data Valid Data Valid Data ...

  • Page 123

    ... Timing tests were performed with a 70-pF capacitor to ground and a 10-KΩ pull-up resistor. For more information on the HSS Jitter Specifications see the Intel Line of Network Processors and IXC1100 Control Plane Processor Developer’s Manual. 5.5.2.9 JTAG Figure 43 ...

  • Page 124

    ... To successfully come out of reset, two things must occur: • Proper power sequence as described in ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 124 ® Intel IXP42X product line and IXC1100 control plane processors JTG_TRST_N T bsr JTG_TMS T T bsrs ...

  • Page 125

    ... A Soft Reset condition is accomplished by the usage of the hardware Watch-Dog Timer module, and software to manage and perform counter updates. For a complete description of Watch-Dog Timer functionality, refer to Watchdog Timer sub-section in the Timers Chapter of the Intel IXC1100 Control Plane Processor Developer’s Manual. The Soft Reset is similar to what is described in that there is no hardware requirement ...

  • Page 126

    ... Reset Timings Figure 45. Reset Timings ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 126 ® Intel IXP42X product line and IXC1100 control plane processors Document Number: 252479-006US August 2006 ...

  • Page 127

    ... V ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Min. Typ. Max. Units Note 2000 µ 500 ns ® before the Intel XScale µs power-up pattern. The CC must be at least POWER_UP at 3.3 V and V at 1.3 V. CCP CC Datasheet 127 ...

  • Page 128

    ... I Notes: 1. Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel IXDP425 / IXCDP1100 Development Platform at room temperature using typical SKU silicon samples. A SmartBits* tester was used in a router application running Linux* on the KIXDP425BD. Two Ethernet NPEs, and two Ethernet controller PCI cards were used in this router application ...

  • Page 129

    ... MHz Notes: 1. Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel IXCDP1100 Development Platform at room temperature using typical SKU silicon samples. A SmartBits* tester was used in a router application running Linux on the KIXDP425BD. Two Ethernet NPEs, and two Ethernet controller PCI cards were used in this router application. Typical case power supply voltages VCC = 1 ...

  • Page 130

    ... MHz Notes: 1. Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel IXCDP1100 Development Platform at room temperature using typical SKU silicon samples. A SmartBits* tester was used in a router application running Linux on the KIXDP425BD. Two Ethernet NPEs, and two Ethernet controller PCI cards were used in this router application. Typical case power supply voltages VCC = 1 ...