MT9HVF12872RHY-667G1 Micron Technology Inc, MT9HVF12872RHY-667G1 Datasheet - Page 12

• Manufacturer Part Number: MT9HVF12872RHY-667G1
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF12872RHY-667G1

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 200VLP SORDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 1Gb
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.215A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

Table 12:
Table 13:
PDF: 09005aef82882ca3/Source: 09005aef82882c52
HVF9C64_128x72RH.fm - Rev. C 1/09 EN
Parameter
DC high-level input
voltage
DC low-level input
voltage
Input voltage
(limits)
Input differential-
pair cross voltage
Input differential
voltage
Input differential
voltage
Input current
Output disabled
current
Static supply
current
Dynamic supply
Input capacitance
Stabilization time
Input clock slew rate
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth (-3db from unity gain)
Parameter
PLL Specifications
CUA845 device or JESD82-21 equivalent
PLL Clock Driver Timing Requirements and Switching Characteristics
Notes:
Symbol
Vid(DC)
Vid(AC)
Iddld
Iodl
Vih
Vin
Idd
Cin
Vix
Vil
Ii
1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC standard JESD82.
OE, OS, CK,
OE, OS, CK,
FBIN, FBIN#
Each input
512MB, 1GB (x72, ECC, SR): 200-Pin DDR2 SDRAM VLP SORDIMM
CK, CK#
OE, OS,
Pins
CK#
CK#
n/a
(not connected to PCB)
OE = L, Vddl = 100mV
CK, CK# = 410 MHz,
Differential input
Differential input
Differential input
Vi = Vddq or Vssq
Vi = Vddq or Vssq
Vi = Vddq or Vssq
all outputs open
CK = CK# = 0pf
Condition
LVCMOS
LVCMOS
12
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Symbol
(Vddq/2) – 0.15
slr(i)
t
0.65 × Vdd
L
Register and PLL Specifications
–250
Min
–0.3
100
–10
0.3
0.6
–
–
–
2
Min
1.0
0.0
30
–
2
©2007 Micron Technology, Inc. All rights reserved.
(Vddq/2) + 0.15
0.35 × Vdd
Vddq + 0.3
Vddq + 0.4
Vddq + 0.4
+250
+500
+300
Max
+10
–
–
3
Max
–0.5
4.0
33
6
–
Units
Units
MHz
V/ns
mA
kHz
µA
µA
µA
µA
pF
µs
%
V
V
V
V
V
V