M25PX16-VMW6G Micron Technology Inc, M25PX16-VMW6G Datasheet - Page 17

• Manufacturer Part Number: M25PX16-VMW6G
• Manufacturer: Micron Technology Inc

Specifications of M25PX16-VMW6G

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SO W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

4.8
Table 3.
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are
As a second level of protection, the Write Protect signal (applied on the W/V
freeze the Status Register in a read-only mode. In this mode, the Block Protect bits (BP2,
BP1, BP0) and the Status Register Write Disable bit (SRWD) are protected. For more
details, see
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in
During the Hold condition, the Serial Data output (DQ1) is high impedance, and Serial Data
input (DQ0) and Serial Clock (C) are Don’t care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
TB
bit
1
1
0.
Status Register
bit 2
contents
BP
1
1
bit 1
Section 6.5: Write Status Register
BP
Protected area sizes
1
1
bit 0
BP
0
1
All sectors (32 sectors: 0 to 31
All sectors (32 sectors: 0 to 31
Figure
6).
Protected area
(WRSR).
Memory content
Figure
none
none
6).
Unprotected area
PP
pin) can
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