M25PX16-VMW6G Micron Technology Inc, M25PX16-VMW6G Datasheet - Page 31

• Manufacturer Part Number: M25PX16-VMW6G
• Manufacturer: Micron Technology Inc

Specifications of M25PX16-VMW6G

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SO W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

6.8
Figure 14. Read Data Bytes at higher speed (FAST_READ) instruction sequence
1. Address bits A23 to A22 are Don’t care.
Dual Output Fast Read (DOFR)
The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at
higher speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin
DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one
doubles the data transfer bandwidth compared to the Read Data Bytes at higher speed
(FAST_READ) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte,
each bit being latched-in during the rising edge of Serial Clock (C). Then the memory
contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency f
during the falling edge of Serial Clock (C).
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole
memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction.
DQ0
DQ1
S
C
DQ0
DQ1
S
C
and data-out sequence
0
7
32 33 34
1
6
High Impedance
Dummy byte
5
2
Instruction
3
4
35
4
3
36 37 38 39 40 41 42 43 44 45 46
2
5
6
1
7
0
MSB
23
7
8
Figure
22 21
6
9 10
24-bit address
DATA OUT 1
5
15.
4
3
28 29 30 31
3
2
2
1
1
0
0
47
MSB
7
6
DATA OUT 2
5
4
3
2
1
0
MSB
AI13737
7
C
,
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