PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 76

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

460EX – PPC460EX Embedded Processor
Table 11. Recommended DC Operating Conditions (Part 2 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Table 12. 3.3V, 2.5V, and LVDS I/O Characteristics
Power Supply Sequencing
All the PPC460EX I/O designs are power supply sequence independent. There is no requirement that the power
supplies power up in any particular order. The following items are power sequence considerations:
76
Ethernet (MII, RGMII), SysClk, SysErr, GPIO00:21
Ethernet (SGMII)
DMA, NAND Flash External Peripheral, UART, USB, Interrupt,
JTAG, TmrClk, Halt , GPIO22:63, Trace
IIC, SPI
PCI
Input Max Allowable Overshoot 2.5V CMOS
Input Max Allowable Overshoot 3.3V LVTTL
Input Max Allowable Undershoot 2.5V CMOS
Input Max Allowable Undershoot 3.3V LVTTL
Output Max Allowable Overshoot 2.5V CMOS
Output Max Allowable Overshoot 3.3V LVTTL
Output Max Allowable Undershoot 2.5V CMOS
Output Max Allowable Undershoot 3.3V LVTTL
Case Temperature
Notes:
• Logic power (V
• I/O power is applied before the logic power is applied: The output driver (connected the balls) comes up in an
1. PCI drivers meet PCI specifications.
2. SV
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltages, but must be filtered before entering the
4. LPDL is least positive down level; MPUL is most positive up level.
5. Case temperature, T
circuitry which ensures the output of the receiver connected to internal chip logic is 0 until the I/O power is
applied. When the logic power is on and the I/O power supplies are off, the I/O logic connected to the
associated ball neither sinks or sources significant current unless influenced by an internal pull-up or pull-down
resistor. While the I/O supply is ramping, the state of the I/O ball is not predictable. This power sequence is not
destructive to the I/Os or internal logic and does not cause any functional problems.
unknown state (driving 1, driving 0, or tri-state) until the internal logic voltage is stable within normal operating
range. This power sequence is not destructive to the I/Os or internal logic and does not cause any functional
problems.
PPC460EX. See “Absolute Maximum Ratings” on page 74.
REF
= SOV
Parameter
DD
/2. SOV
DD
Interfaces
) is applied before the I/O supply voltages: The I/Os include internal supply sequencing
C
, is measured at top center of case surface with device soldered to a circuit board.
DD
= + 1.8V for DDR2 memory or + 2.5V for DDR1 memory.
V
V
V
V
Symbol
V
V
V
V
OMAO25
OMAO33
OMAU25
OMAU33
IMAO25
IMAO33
IMAU25
IMAU33
T
C
3.3V tolerant 2.5V CMOS
Minimum
3.3V LVTTL
3.3V LVTTL
1.8V LVDS
− 0.6
− 0.6
− 0.6
− 0.6
− 40
3.3V
I/O
Typical
Output Impedance
Preliminary Data Sheet
Revision 1.19 – June 17, 2009
( Ω )
50
50
35
-
-
Maximum
+ 3.9
+ 3.9
+ 3.9
+ 3.9
+ 85
Input Capacitance
AMCC Proprietary
Unit
° C
V
V
V
V
V
V
V
V
(pF)
5.7
5.0
5.2
5.2
5.7
Notes
6