PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 94

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

460EX – PPC460EX Embedded Processor
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 9. DDR SDRAM Write Cycle Timing
Note: The timing data in the following tables is based on simulation runs using Einstimer.
Table 26. I/O Timing—DDR SDRAM T
Notes:
1. All of the DQS signals are referenced to MemClkOut.
2. MemClkOut frequency is 200MHz.
94
DQS0:8/ DQS0:8
Signal Name
MemClkOut
T
T
T
T
T
MemData
SA
SD
HD
Addr/Cmd
HA
DS
PLB Clk
= Setup time for address and command signals to MemClkOut
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Hold time for address and command signals from MemClkOut
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
DQS
DS
T
SA
for 200 MHz
T
HA
T
SD
T
Minimum
DS
T
HD
4.9
T
T
DS
SD
T
(ns)
HD
Preliminary Data Sheet
Revision 1.19 – June 17, 2009
Maximum
5.1
AMCC Proprietary