PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 93

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

Revision 1.19 – June 17, 2009
DDR SDRAM Timing Conditions
The following timing values are generated by means of simulation and includes logic, driver, package RLC, and
lengths. Values are calculated over best case and worst case processes with speed, junction temperature, and
voltage as follows:
Figure 8. DDR SDRAM Simulation Signal Termination Model
DDR SDRAM Write Operation
The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes.
Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and
maximum values are measured under worst case conditions. The timing numbers in the following sections are
obtained using a simulation that assumes a model as shown in Figure 8.
AMCC Proprietary
Table 25. DDR SDRAM Operation Conditions
Preliminary Data Sheet
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
Worst
Case
Best
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
PPC460EX
Process Speed
Addr/Ctrl (DDR2)
Addr/Ctrl/Data/DQS/DM (DDR1)
MemClkOut
MemClkOut
Slow
Fast
Case Temperature (°C)
− 40
+ 85
460EX – PPC460EX Embedded Processor
10 pF
10 pF
SOV DD for DDR1 (V)
V
+ 2.4
+ 2.6
120 Ω
TT
50Ω
30pF
= SOV
DD
/2
SOV DD for DDR2 (V)
+ 1.9
+ 1.7
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