ST72F324BK6TAS STMicroelectronics, ST72F324BK6TAS Datasheet - Page 100

• Manufacturer Part Number: ST72F324BK6TAS
• Description: 8-BIT MCU
• Manufacturer: STMicroelectronics

On-chip peripherals
Note:
Caution:
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Figure 50. Generic SS timing diagram
Figure 51. Hardware/software slave select management
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1.
2.
3.
If the SPICSR register is not written first, the SPICR register setting (MSTR bit) might not be
taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
Collision error will occur when the slave writes to the shift register
error (WCOL) on page
Write to the SPICR register:
–
–
Write to the SPICSR register:
–
Write to the SPICR register:
–
Select the clock frequency by configuring the SPR[2:0] bits.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 52
Note: The slave must have the same CPOL and CPHA settings as the master.
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
Set the MSTR and SPE bits.
Note: MSTR and SPE bits remain set only if SS is high.
MOSI/MISO
Master SS
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
shows the four possible configurations.
SS external pin
103).
Doc ID13466 Rev 4
SSI bi
Byte 1
t
SSM bit
1
0
Byte 2
SS internal
Byte 3
(seeWrite collision
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