EPM2210F256C4 Altera, EPM2210F256C4 Datasheet - Page 15

• Manufacturer Part Number: EPM2210F256C4
• Description: IC MAX II CPLD 2210 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM2210F256C4

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of I /o: 204
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 2210
• Family Name: MAX II
• # Macrocells: 1700
• Frequency (max): 2.3148GHz
• Propagation Delay Time: 9.1ns
• Number Of Logic Blocks/elements: 221
• # I/os (max): 204
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1340; EPM2210F256C4

Chapter 2: MAX II Architecture
Logic Elements
Figure 2–6. MAX II LE
© October 2008 Altera Corporation
Reset (DEV_CLRn)
labpre/aload
labclkena1
labclkena2
Chip-Wide
labclk1
labclk2
labclr1
labclr2
data1
data2
data3
data4
addnsub
Each LE’s programmable register can be configured for D, T, JK, or SR operation. Each
register has data, true asynchronous load data, clock, clock enable, clear, and
asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any
LE can drive the register’s clock and clear control signals. Either general-purpose I/O
pins or LEs can drive the clock enable, preset, asynchronous load, and asynchronous
data. The asynchronous load data input comes from the data3 input of the LE. For
combinational functions, the LUT output bypasses the register and drives directly to
the LE outputs.
Each LE has three outputs that drive the local, row, and column routing resources. The
LUT or register output can drive these three outputs independently. Two LE outputs
drive column or row and DirectLink routing connections and one drives local
interconnect resources. This allows the LUT to drive one output while the register
drives another output. This register packing feature improves device utilization
because the device can use the register and the LUT for unrelated functions. Another
special packing mode allows the register output to feed back into the LUT of the same
LE so that the register is packed with its own fan-out LUT. This provides another
mechanism for improved fitting. The LE can also drive out registered and
unregistered versions of the LUT output.
Clock Enable
Asynchronous
Clear/Preset/
Load Logic
Clock and
LAB Carry-In
Select
Carry-In1
Carry-In0
Look-Up
Table
(LUT)
Chain
Carry
Register chain
routing from
previous LE
Carry-Out0
Carry-Out1
LAB Carry-Out
Synchronous
LAB-wide
Synchronous
Load
Clear Logic
Load and
Synchronous
LAB-wide
Clear
Register Bypass
Packed
Register Select
ADATA
D
ENA
PRN/ALD
CLRN
Register
Feedback
Q
Programmable
Register
MAX II Device Handbook
LUT chain
routing to next LE
Row, column,
and DirectLink
routing
Row, column,
and DirectLink
routing
Local routing
Register chain
output
2–7