XC56309AG100A Freescale Semiconductor, XC56309AG100A Datasheet - Page 176

• Manufacturer Part Number: XC56309AG100A
• Description: IC DSP 24BIT 100MHZ 144-TQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309AG100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Communication Interface (SCI)
back as it is received. After both numbers are loaded, the program size is in A0 and the starting
address is in A1.
The program is then loaded one byte at a time, least significant byte first. After the program is
loaded, the operating mode is set to zero, the CCR is cleared, and the DSP begins execution with
the first instruction loaded.
8.5 Exceptions
The SCI can cause five different exceptions in the DSP, discussed here from the highest to the
lowest priority:
8.6 SCI Programming Model
The SCI programming model can be viewed as three types of registers:
8-8
1.
2.
3.
4.
5.
Control
— SCI Control Register (SCR) in Figure 8-3
— SCI Clock Control Register (SCCR) in Figure 8-4
Status
— SCI Status Register (SSR) in Figure 8-3
Data transfer
— SCI Receive Data Registers (SRX) in Figure 8-7
— SCI Transmit Data Registers (STX) in Figure 8-7
SCI receive data with exception status occurs when the receive data register is full with
a receiver error (parity, framing, or overrun error). To clear the pending interrupt, read
the SCI status register; then read SRX. Use a long interrupt service routine to handle the
error condition. This interrupt is enabled by SCR[16] (REIE).
SCI receive data occurs when the receive data register is full. Read SRX to clear the
pending interrupt. This error-free interrupt can use a fast interrupt service routine for
minimum overhead. This interrupt is enabled by SCR[11] (RIE).
SCI transmit data occurs when the transmit data register is empty. Write STX to clear
the pending interrupt. This error-free interrupt can use a fast interrupt service routine for
minimum overhead. This interrupt is enabled by SCR[12] (TIE).
SCI idle line occurs when the receive line enters the idle state (10 or 11 bits of ones).
This interrupt is latched and then automatically reset when the interrupt is accepted.
This interrupt is enabled by SCR[10] (ILIE).
SCI timer occurs when the baud rate counter reaches zero. This interrupt is
automatically reset when the interrupt is accepted. This interrupt is enabled by SCR[13]
(TMIE).
DSP56309 User’s Manual, Rev. 1
Freescale Semiconductor