KMSC8122TVT6400V Freescale Semiconductor, KMSC8122TVT6400V Datasheet - Page 20

• Manufacturer Part Number: KMSC8122TVT6400V
• Description: DSP 16BIT QUAD CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of KMSC8122TVT6400V

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
Table 11 summarizes the reset actions that occur as a result of the different reset sources.
2.5.4.1
Asserting
V
2.5.4.2
The MSC8122 has two mechanisms for writing the reset configuration:
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on
Configuration Mode and boot and operating conditions:
20
Configuration pins sampled (Refer to
Section 2.5.4.1 for details).
SPLL state reset
System reset configuration write through
the DSI
System reset configuration write though
the system bus
HRESET driven
SIU registers reset
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and
GPIO)
SRESET driven
SC140 extended cores reset
MQBS reset
DD
•
•
•
•
•
•
•
•
•
•
and
Reset Action/Reset Source
V
Through the direct slave interface (DSI)
Through the system bus. When the reset configuration is written through the system bus, the MSC8122 acts as a
configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is
written, a default configuration word is applied.
RSTCONF
CNFGS
DSISYNC
DSI64
CHIP_ID[0–3]
BM[0–2]
SWTE
MODCK[1–2]
PORESET
DDH
are both at their nominal levels.
Power-On Reset (PORESET) Pin
Reset Configuration
initiates the power-on reset flow.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Table 11. Reset Actions for Each Reset Source
External only
(PORESET)
Power-On
Reset
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PORESET
(Software Watchdog or
Hard Reset (HRESET)
External or Internal
Bus Monitor)
must be asserted externally for at least 16
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
PORESET
External
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Soft Reset (SRESET)
deassertion to define the Reset
Freescale Semiconductor
EXTEST, CLAMP, or
Depends on command
JTAG Command:
CLKIN
HIGHZ
Yes
Yes
Yes
No
No
No
No
No
No
cycles after