KMSC8122TVT6400V Freescale Semiconductor, KMSC8122TVT6400V Datasheet - Page 21

• Manufacturer Part Number: KMSC8122TVT6400V
• Description: DSP 16BIT QUAD CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of KMSC8122TVT6400V

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.5.4.3
Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or
through the system bus.
Freescale Semiconductor
Note:
No.
1
2
3
5
6
7
8
Required external PORESET duration minimum
•
•
•
•
Delay from deassertion of external PORESET to deassertion of internal
PORESET
•
Delay from de-assertion of internal PORESET to SPLL lock
•
•
•
•
Delay from SPLL to HRESET deassertion
•
Delay from SPLL lock to SRESET deassertion
•
Setup time from assertion of
CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of
PORESET
Hold time from deassertion of PORESET to deassertion of
CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and
MODCK[1–2]
Timings are not tested, but are guaranteed by design.
Output (I/O)
CLKIN = 20 MHz
CLKIN = 100 MHz (300 MHz core)
CLKIN = 133 MHz (400 MHz core)
CLKIN = 166 MHz (500 MHz core)
CLKIN = 20 MHz to 166 MHz
CLKIN = 20 MHz (RDF = 1)
CLKIN = 100 MHz (RDF = 1) (300 MHz core)
CLKIN = 133 MHz (RDF = 2) (400 MHz core)
CLKIN = 166 MHz (RDF = 2) (500 MHz core)
REFCLK = 40 MHz to 166 MHz
REFCLK = 40 MHz to 166 MHz
Output (I/O)
PORESET
HRESET
SRESET
PORESET
Input
Table 12. Timing for a Reset Configuration Write through the DSI or System Bus
Internal
Reset Timing Tables
Figure 9. Timing Diagram for a Reset Configuration Write
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
1
Characteristics
RSTCONF
Reset configuration write
sequence during this
period.
RSTCONF, CNFGS, DSISYNC, DSI64
CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]
pins are sampled
Reset Configuration
, CNFGS, DSISYNC, DSI64,
Host programs
1 + 2
Word
2
RSTCONF
SPLL
locking period
MODCK[3–5]
,
3
clock-division factor)
6400/(CLKIN/RDF)
(PLL reference
Expression
512/REFCLK
515/REFCLK
1024/CLKIN
16/CLKIN
SPLL is locked
(no external indication)
Electrical Characteristics
5
6
6.17
3.08
3.10
Min
800
160
120
320
96
64
96
77
3
5
12.88
Max
51.2
12.8
320
64
96
77
—
—
—
—
—
—
Unit
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
21