KMSC8122TVT6400V Freescale Semiconductor, KMSC8122TVT6400V Datasheet - Page 41

• Manufacturer Part Number: KMSC8122TVT6400V
• Description: DSP 16BIT QUAD CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of KMSC8122TVT6400V

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 34. For optimal noise filtering, place the circuit as close as possible to
to
kept short and direct. Provide an extremely low impedance path to the ground plane for
by a 0.01-µF capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of
the PCB aligned with the depopulated void on the MSC8122 located in the square defined by positions, L11, L12, L13, M11,
M12, M13, N11, N12, and N13.
3.3
Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to
V
Freescale Semiconductor
DDH
V
CCSYN
•
•
•
•
•
•
•
•
•
•
•
or
GND
If the DSI is unused (DDR[DSIDIS] is set),
disconnected.
When the DSI uses synchronous mode,
up or down, depending on design requirements.
HDST
DCR[DSRFA] bit is set.
When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up
HDBE[1–3]
When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared,
must be pulled up.
When the DSI is in asynchronous mode,
When the DSI uses sliding window address mode (DCR[SLDWA] = 1), the external HA[11–13] signals must be
connected (tied) to the correct voltage levels so that the host can perform the first access to the DCR. After reset, the
DSI expects full address mode (DCR[SLDWA] = 0). The DCR address in the DSI memory map is 0x1BE000, which
requires the following connections:
— HA11 must be pulled high (1)
— HA12 must be pulled high (1)
— HA13 must be pulled low (0)
The following signals must be pulled up:
In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):
—
—
—
—
If there is an external bus master (BCR[EBM] = 1):
—
—
In single-master mode,
modes, they must be pulled up.
, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to
Connectivity Guidelines
BG
EXT_BG[2–3]
functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.
BR
EXT_BR[2–3]
BR
EXT_BR[2–3]
functionality.
, except for the following:
can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the
,
,
must be pulled up.
DBG
BG
,
and
DBG
, and
HWBS[4–7]
, and
,
,
TS
must be pulled up if multiplexed to the system bus functionality.
EXT_BG[2–3]
EXT_DBG[2–3]
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
can be left unconnected.
TS
ABB
V
must be pulled up.
DD
/
and
HDBS[4–7]
10Ω
DBB
, and
, and
can be selected as
Figure 34. V
EXT_DBG[2–3]
/
HTA
HWBE[4–7]
GBL
HBRST
10nH
HRESET
HCS
must be pulled up. In asynchronous mode,
can be left unconnected if they are multiplexed to the system bus
10 µF
and
and
,
SRESET
/
CCSYN
HDBE[4–7]
HCLKIN
HBCS
must be pulled up if multiplexed to the system bus
IRQ
Bypass
,
inputs and be connected to the non-active value. In other
must pulled up and all the rest of the DSI signals can be
ARTRY
should either be disconnected or pulled up.
/
PWE[4–7]
V
HWBS[1–3]
,
CCSYN
TA
0.01 µF
,
TEA
V
/
. The 0.01-µF capacitor should be closest
PSDDQM[4–7]
CCSYN
HWBS[1–3]
,
GND
PSDVAL
/
HDBS[1–3]
Hardware Design Considerations
SYN
V
. Bypass
HTA
/
, and
DD
HDBS[1–3]
/
PBS[4–7]
. These traces should be
/
should be pulled either
HWBE[1–3]
AACK
GND
.
/
.
HWBE[1–3]
SYN
/
HDBE[1–3]
to
V
CCSYN
/
41