IC DSP CONTROLLER 16BIT 68PLCC

ADSP-2104BP-80

Manufacturer Part NumberADSP-2104BP-80
DescriptionIC DSP CONTROLLER 16BIT 68PLCC
ManufacturerAnalog Devices Inc
SeriesADSP-21xx
TypeFixed Point
ADSP-2104BP-80 datasheet
 


Specifications of ADSP-2104BP-80

Rohs StatusRoHS non-compliantInterfaceSynchronous Serial Port (SSP)
Clock Rate20MHzNon-volatile MemoryExternal
On-chip Ram1.5kBVoltage - I/o5.00V
Voltage - Core5.00VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case68-PLCC
Device Core Size16bArchitectureEnhanced Harvard
FormatFixed PointClock Freq (max)20MHz
Mips20Device Input Clock Speed20MHz
Ram Size512ByteProgram Memory Size8KB
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count68
Package TypePLCC  
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SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus & Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator, and Shifter
Single-Cycle Instruction Execution & Multifunction
Instructions
On-Chip Program Memory RAM or ROM
& Data Memory RAM
Integrated I/O Peripherals: Serial Ports and Timer
FEATURES
20 MIPS, 50 ns Maximum Instruction Rate
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory (e.g., EPROM )
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering, and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PLCC Package
GENERAL DESCRIPTION
The ADSP-2104 and ADSP-2109 processors are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-2104/ADSP-2109 processors are built upon a common
core. Each processor combines the core DSP architecture—
computation units, data address generators, and program
sequencer—with differentiating features such as on-chip
program and data memory RAM (ADSP-2109 contains 4K
words of program ROM), a programmable timer, and two
serial ports.
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the ADSP-2104/ADSP-2109 operates at
20 MIPS with a 50 ns instruction cycle time. The ADSP-2104L
and ADSP-2109L are 3.3 volt versions which operate at
13.824 MIPS with a 72.3 ns instruction cycle time. Every
instruction can execute in a single cycle. Fabrication in CMOS
results in low power dissipation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Low Cost DSP Microcomputers
ADSP-2104/ADSP-2109
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
PROGRAM
GENERATORS
SEQUENCER
DAG 1
DAG 2
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
SERIAL PORTS
MAC
SHIFTER
ALU
SPORT 0
ADSP-2100 CORE
The ADSP-2100 Family’s flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-2104/ADSP-2109 can perform all
of the following operations:
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computation
Receive and transmit data via one or two serial ports
The ADSP-2104 contains 512 words of program RAM, 256
words of data RAM, an interval timer, and two serial ports.
The ADSP-2104L is a 3.3 volt power supply version of the
ADSP-2104; it is identical to the ADSP-2104 in all other
characteristics.
The ADSP-2109 contains 4K words of program ROM and
256 words of data RAM, an interval timer, and two serial ports.
The ADSP-2109L is a 3.3 volt power supply version of the
ADSP-2109; it is identical to the ADSP-2109 in all other
characteristics.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
MEMORY
PROGRAM
DATA
MEMORY
MEMORY
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
TIMER
SPORT 1
© Analog Devices, Inc., 1996
Fax: 617/326-8703

ADSP-2104BP-80 Summary of contents

  • Page 1

    ... Receive and transmit data via one or two serial ports The ADSP-2104 contains 512 words of program RAM, 256 words of data RAM, an interval timer, and two serial ports. The ADSP-2104L is a 3.3 volt power supply version of the ADSP-2104 identical to the ADSP-2104 in all other characteristics. ...

  • Page 2

    ... Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 6 Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Boot Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . . 8 ADSP-2109 Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Procedure for ADSP-2109 ROM Processors . . . . 9 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPECIFICATIONS (ADSP-2104/ADSP-2109 Recommended Operating Conditions . . . . . . . . . . . . . . . . 12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Dissipation Example ...

  • Page 3

    ... External devices can gain control of the processor’s buses with the use of the bus request/grant signals (BR, BG). One bus grant execution mode (GO Mode) allows the ADSP- 2104/ADSP-2109 to continue running from internal memory. A second execution mode requires the processor to halt while buses are granted. – ...

  • Page 4

    ... Booting circuitry provides for loading on-chip program memory automatically from byte-wide external memory. After reset, three wait states are automatically generated. This allows, for example, the ADSP-2104 to use a 150 ns EPROM as external boot memory. Multiple programs can be selected and loaded from the EPROM with no additional hardware. ...

  • Page 5

    ... Table II shows pin definitions for the ADSP-2104/ADSP-2109 processors. Any inputs not used must be tied to V SYSTEM INTERFACE Figure 3 shows a typical system for the ADSP-2104/ADSP-2109, with two serial I/O devices, a boot EPROM, and optional external program and data memory. A total of 14.25K words of data memory and 14 ...

  • Page 6

    ... RFS1 or IRQ0 TFS1 or IRQ1 DT1 or FO DR1 or FI SPORT 0 PMS SCLK0 RFS0 TFS0 DMS DT0 DR0 ) ARE USED TO SUPPLY THE TWO MSBs OF THE 23-22 Figure 3. ADSP-2104/ADSP-2109 System –6– A 13-0 BOOT D 23-22 ADDR MEMORY e.g. EPROM D 15-8 2764 DATA 27128 OE 27256 ...

  • Page 7

    ... Program Memory Maps Program memory can be mapped in two ways, depending on the state of the MMAP pin. Figure 4 shows the ADSP-2104 program memory maps. Figure 5 shows the program memory maps for the ADSP-2109. 0x0000 INTERNAL RAM 512 WORDS LOADED FROM EXTERNAL BOOT MEMORY ...

  • Page 8

    ... The boot memory interface can generate zero to seven wait states; it defaults to three wait states after RESET. This allows the ADSP-2104 to boot from a single low cost EPROM such as a 27C256. Program memory is booted one byte at a time and converted to 24-bit program memory words. ...

  • Page 9

    ... This can be overcome by locating program memory data in on-chip memory. Ordering Procedure for ADSP-2109 ROM Processor To place an order for a custom ROM-coded ADSP-2109, you must: 1. Complete the following forms contained in the ADSP ROM Ordering Package, available from your Analog Devices sales ...

  • Page 10

    ... Multifunction instructions perform one or two data moves and a computation. The instruction set is summarized below. The ADSP-2100 Family Users Manual contains a complete reference to the instruction set. Add/Add with Carry Subtract X – ...

  • Page 11

    ... MF=MX0 * MY1 ( RND), MX0=DM(I2,M1); MR=MX0 * MF ( RND), AY0=PM(I6,M5); DO adapt UNTIL CE; AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7); adapt: PM(I6,M6 MR=MX0 * MF ( RND); MODIFY(I2,M3); MODIFY(I6,M7); REV. 0 ADSP-2104/ADSP-2109 Do Until Loop Jump Call Subroutine Jump/Call on Flag In Pin Modify Flag Out Pin Return from Subroutine Return from Interrupt Service Routine Idle ...

  • Page 12

    ... Three-state pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0. 5 Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0 BR, CLKIN Active (to force three-state condition). 7 Although specified for TTL outputs, all ADSP-2104/ADSP-2109 outputs are CMOS-compatible and will drive Guaranteed but not tested. 9 Applies to PGA, PLCC, PQFP package types. 10 Output pin capacitance is the capacitive load for any three-stated output pin ...

  • Page 13

    ... Supply Current (Idle) DD NOTES 1 Current reflects device operating with no output loads 0.4 V and 2 Idle refers to ADSP-2104/ADSP-2109 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V For typical supply current (internal power dissipation) figures, see Figure 55mW 50 40 38mW 30 28mW ...

  • Page 14

    ... load capacitance output switching frequency. Example ADSP-2104 application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. • ...

  • Page 15

    ... SPECIFICATIONS (ADSP-2104/ADSP-2109) TEST CONDITIONS Figure 10 shows voltage reference levels for ac measurements. INPUT OUTPUT Figure 10. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state ...

  • Page 16

    ... ADSP-2104L/ADSP-2109L–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Supply Voltage DD T Ambient Operating Temperature AMB See “Environmental Conditions” for information on thermal specifications. ELECTRICAL CHARACTERISTICS Parameter Hi-Level Input Voltage Lo-Level Input Voltage Hi-Level Output Voltage Lo-Level Output Voltage Hi-Level Input Current Lo-Level Input Current ...

  • Page 17

    ... Supply Current (Dynamic Supply Current (Idle) DD NOTES 1 Current reflects device operating with no output loads 0.4 V and 2 Idle refers to ADSP-2104L/ADSP-2109L state of operation during execution of IDLE instruction. Deasserted pins are driven to either V For typical supply current (internal power dissipation) figures, see Figure 13 9mW 6mW 5mW ...

  • Page 18

    ... load capacitance output switching frequency. Example ADSP-2104L application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. • ...

  • Page 19

    ... SPECIFICATIONS (ADSP-2104L/ADSP-2109L) TEST CONDITIONS Figure 16 shows voltage reference levels for ac measurements. INPUT OUTPUT Figure 16. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state ...

  • Page 20

    ... Timing requirements guarantee that the processor operates correctly with other devices. MEMORY REQUIREMENTS The table below shows common memory device specifications and the corresponding ADSP-2104/ADSP-2109 timing parameters, for your convenience. ADSP-2104/ADSP-2109 Timing Timing ...

  • Page 21

    ... TIMING PARAMETERS (ADSP-2104/ADSP-2109) CLOCK SIGNALS & RESET Parameter Timing Requirement: t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH t RESET Width Low RSP Switching Characteristic: t CLKOUT Width Low CPL t CLKOUT Width High CPH t CLKIN High to CLKOUT High CKOH NOTE 1 Applies after powerup sequence is complete ...

  • Page 22

    ... IFS IFH during the following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further information on interrupt servicing.) 3 Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced. ...

  • Page 23

    ... TIMING PARAMETERS (ADSP-2104/ADSP-2109) BUS REQUEST/GRANT Parameter Timing Requirement Hold after CLKOUT High Setup before CLKOUT Low BS Switching Characteristic: t CLKOUT High to DMS, SD PMS, BMS, RD, WR Disable t DMS, PMS, BMS, RD, WR SDB Disable to BG Low t BG High to DMS, PMS, SE BMS, RD, WR Enable t DMS, PMS, BMS, RD, WR ...

  • Page 24

    ... ADSP-2104/ADSP-2109 TIMING PARAMETERS (ADSP-2104/ADSP-2109) MEMORY READ Parameter Timing Requirement Low to Data Valid RDD t A0–A13, PMS, DMS, BMS to Data Valid AA t Data Hold from RD High RDH Switching Characteristic Pulse Width RP t CLKOUT High to RD Low CRD t A0–A13, PMS, DMS, BMS Setup before ...

  • Page 25

    ... TIMING PARAMETERS (ADSP-2104/ADSP-2109) MEMORY WRITE Parameter Switching Characteristic: t Data Setup before WR High DW t Data Hold after WR High Pulse Width Low to Data Enabled WDE t A0–A13, DMS, PMS Setup before ASW WR Low t Data Disable before Low DDR t CLKOUT High to WR Low CWR t A0– ...

  • Page 26

    ... ADSP-2104/ADSP-2109 TIMING PARAMETERS (ADSP-2104/ADSP-2109) SERIAL PORTS Parameter Timing Requirement: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristic: t CLKOUT High to SCLK CC OUT t SCLK High to DT Enable SCDE t SCLK High to DT Valid ...

  • Page 27

    ... Timing requirements guarantee that the processor operates correctly with other devices. MEMORY REQUIREMENTS The table below shows common memory device specifications and the corresponding ADSP-2104L/ADSP-2109L timing parameters, for your convenience. ADSP-2104L/ADSP-2109L Timing Parameter Timing Parameter Definition t A0– ...

  • Page 28

    ... ADSP-2104/ADSP-2109 TIMING PARAMETERS (ADSP-2104L/ADSP-2109L) CLOCK SIGNALS & RESET Parameter Timing Requirement: t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH t RESET Width Low RSP Switching Characteristic: t CLKOUT Width Low CPL t CLKOUT Width High CPH t CLKIN High to CLKOUT High CKOH ...

  • Page 29

    ... IFS IFH following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further information on interrupt servicing.) 3 Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced. ...

  • Page 30

    ... ADSP-2104/ADSP-2109 TIMING PARAMETERS (ADSP-2104L/ADSP-2109L) BUS REQUEST/GRANT Parameter Timing Requirement Hold after CLKOUT High Setup before CLKOUT Low BS Switching Characteristic: t CLKOUT High to DMS, PMS, BMS, RD, WR Disable SD t DMS, PMS, BMS, RD, WR Disable to BG Low SDB t BG High to DMS, PMS, BMS, RD, WR Enable ...

  • Page 31

    ... TIMING PARAMETERS (ADSP-2104L/ADSP-2109L) MEMORY READ Parameter Timing Requirement Low to Data Valid RDD t A0–A13, PMS, DMS, BMS to Data Valid AA t Data Hold from RD High RDH Switching Characteristic Pulse Width RP t CLKOUT High to RD Low CRD t A0–A13, PMS, DMS, BMS Setup before RD Low ...

  • Page 32

    ... ADSP-2104/ADSP-2109 TIMING PARAMETERS (ADSP-2104L/ADSP-2109L) MEMORY WRITE Parameter Switching Characteristic: t Data Setup before WR High DW t Data Hold after WR High Pulse Width Low to Data Enabled WDE t A0–A13, DMS, PMS Setup before WR Low ASW t Data Disable before Low DDR t CLKOUT High to WR Low ...

  • Page 33

    ... TIMING PARAMETERS (ADSP-2104L/ADSP-2109L) SERIAL PORTS Parameter Timing Requirement: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP in Switching Characteristic: t CLKOUT High to SCLK CC out t SCLK High to DT Enable SCDE t SCLK High to DT Valid ...

  • Page 34

    ... D19 28 12 D20 29 13 D21 30 14 D22 31 15 D23 MMAP 34 PIN CONFIGURATIONS 68-Lead PLCC GND 10 PIN 1 IDENTIFIER D19 11 D20 12 D21 13 D22 14 D23 15 ADSP-2104 ADSP-2104L ADSP-2109 17 ADSP-2109L BR 18 TOP VIEW IRQ2 19 (PINS DOWN Pin PLCC Number Name BR 35 IRQ2 36 RESET GND ...

  • Page 35

    ... ADSP-2104/ADSP-2109 BOTTOM VIEW (PINS UP) MILLIMETERS TYP MAX 4.29 14.37 4.45 12.64 0.43 10.46 ...

  • Page 36

    ... ADSP-2104/ADSP-2109 Part Number* ADSP-2104KP-80 ADSP-2109KP-80 ADSP-2104LKP-55 ADSP-2109LKP- Commercial Temperature Range ( +70 C PLCC (Plastic Leaded Chip Carrier). ORDERING GUIDE Ambient Temperature Instruction Range Rate +70 C 20.0 MHz +70 C 20.0 MHz +70 C 13.824 MHz +70 C 13.824 MHz –36– Package Package Description Option ...