EP2C70F672C8N Altera, EP2C70F672C8N Datasheet - Page 158

• Manufacturer Part Number: EP2C70F672C8N
• Description: IC CYCLONE II FPGA 70K 672-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C70F672C8N

• Number Of Logic Elements/cells: 68416
• Number Of Labs/clbs: 4276
• Total Ram Bits: 1152000
• Number Of I /o: 422
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• No. Of Logic Blocks: 4276
• Family Type: Cyclone II
• No. Of I/o's: 422
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 320MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 68416
• # I/os (max): 422
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 68416
• Ram Bits: 1152000
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• For Use With: P0304 - DE2-70 CALL FOR ACADEMIC PRICING544-1703 - VIDEO KIT W/CYCLONE II EP2C70N544-1699 - DSP KIT W/CYCLONE II EPS2C70N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1688

Duty Cycle Distortion
Figure 5–9. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
5–68
Cyclone II Device Handbook, Volume 1
clk
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the
corresponding I/O element (IOE) block. When the output is a single data
rate signal (non-DDIO), only one edge of the register input clock (positive
or negative) triggers output transitions
present on the input clock signal, or caused by the clock input buffer, or
different input I/O standard, does not transfer to the output signal.
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions
clock and the input clock buffer affect the output DCD.
IOE
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
(Figure
DFF
D
5–10). Therefore, any distortion on the input
Q
(Figure
5–9). Therefore, any DCD
Altera Corporation
output
February 2008