EP2C70F672C8N Altera, EP2C70F672C8N Datasheet - Page 31

• Manufacturer Part Number: EP2C70F672C8N
• Description: IC CYCLONE II FPGA 70K 672-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C70F672C8N

• Number Of Logic Elements/cells: 68416
• Number Of Labs/clbs: 4276
• Total Ram Bits: 1152000
• Number Of I /o: 422
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• No. Of Logic Blocks: 4276
• Family Type: Cyclone II
• No. Of I/o's: 422
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 320MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 68416
• # I/os (max): 422
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 68416
• Ram Bits: 1152000
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• For Use With: P0304 - DE2-70 CALL FOR ACADEMIC PRICING544-1703 - VIDEO KIT W/CYCLONE II EP2C70N544-1699 - DSP KIT W/CYCLONE II EPS2C70N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1688

Figure 2–12. EP2C15 & Larger PLL, CLK[], DPCLK[] & Clock Control Block Locations
Notes to
(1)
(2)
Altera Corporation
February 2007
There are four clock control blocks on each side.
Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time. The other CDPCLK pins
can be used as general-purpose I/O pins.
CDPCLK0
CDPCLK1
CLK[3..0]
Figure
DPCLK0
DPCLK1
2–12:
4
PLL 3
PLL 1
4
3
CDPCLK7
CDPCLK2
(2)
(2)
Clock Control
DPCLK[11..10]
Block (1)
3
DPCLK[3..2]
4
GCLK[15..0]
2
16
2
CLK[15..12]
CLK[11..8]
16
16
4
4
GCLK[15..0]
16
DPCLK[9..8]
DPCLK[5..4]
2
2
Clock Control
Block (1)
3
4
Cyclone II Device Handbook, Volume 1
CDPCLK6
CDPCLK3
(2)
(2)
3
PLL 4
PLL 2
4
Cyclone II Architecture
4
CDPCLK5
DPCLK7
CLK[7..4]
DPCLK6
CDPCLK4
2–19