EP2SGX30DF780I4N Altera, EP2SGX30DF780I4N Datasheet - Page 16

IC STRATIX II GX 30K 780-FBGA

EP2SGX30DF780I4N

Manufacturer Part Number
EP2SGX30DF780I4N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX30DF780I4N

Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2177

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Transceivers
2–8
Stratix II GX Device Handbook, Volume 1
Note to
(1)
Fabric to PCS data path width (bits)
Data rate range (Gbps)
PCS to PMA data path width (bits)
Byte ordering
Data symbol A (MSB)
Data symbol B
Data symbol C
Data symbol D (LSB)
Table 2–4. Data Path Configurations
Designs can use byte ordering when byte serialization and deserialization are used.
Table
Parameter
2–4:
(1)
Table 2–4
in single-width and double-width modes.
1
8B/10B Encoder
There are two different modes of operation for 8B/10B encoding.
Single-width (8-bit) mode supports natural data rates from 622 Mbps to
3.125 Gbps. Double-width (16-bit cascaded) mode supports data rates
above 3.125 Gbps. The encoded data has a maximum run length of five.
The 8B/10B encoder can be bypassed.
encoding process.
Deserialization
Note (1)
Serialization/
Refer to the section
description of the single- and double-width modes.
Without Byte
shows the data path configurations for the Stratix II GX device
0.6 to 2.5
8 or 10
8 or 10
v
Single-Width Mode
Deserialization
Serialization/
0.6 to 3.125
With Byte
16 or 20
8 or 10
“8B/10B Encoder” on page 2–8
v
v
v
Figure 2–5
Deserialization
Serialization/
Without Byte
16 or 20
16 or 20
1 to 5.0
v
v
Double-Width Mode
diagrams the 10-bit
Altera Corporation
Deserialization
Serialization/
October 2007
With Byte
1 to 6.375
for a
32 or 40
16 or 20
v
v
v
v
v

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