EP2S30F672I4 Altera, EP2S30F672I4 Datasheet - Page 178

IC STRATIX II FPGA 30K 672-FBGA

EP2S30F672I4

Manufacturer Part Number
EP2S30F672I4
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S30F672I4

Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1899
EP2S30F672I4

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S30F672I4
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S30F672I4
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S30F672I4
Manufacturer:
ALTERA
0
Part Number:
EP2S30F672I4N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672I4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S30F672I4N
Manufacturer:
XILINX
0
Part Number:
EP2S30F672I4N
Manufacturer:
ALTERA
0
Part Number:
EP2S30F672I4N
0
Timing Model
5–42
Stratix II Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
Table 5–44. EP2S15 Column Pins Regional Clock Timing Parameters
Table 5–45. EP2S15 Column Pins Global Clock Timing Parameters
Table 5–46. EP2S15 Row Pins Regional Clock Timing Parameters
Parameter
Parameter
Parameter
Industrial
Industrial
Industrial
-0.053
-0.063
-0.109
-0.104
1.445
1.288
0.104
1.419
1.262
0.094
1.232
1.237
Minimum Timing
Minimum Timing
Minimum Timing
EP2S15 Clock Timing Parameters
Tables 5–44
EP2S15 devices.
1.487
1.322
0.092
-0.073
Commercial
Commercial
Commercial
-0.063
-0.122
-0.117
1.512
1.347
0.102
1.288
1.293
though
5–47
2.456
2.214
0.326
0.084
-3 Speed
-3 Speed
-3 Speed
show the maximum clock timing parameters for
Grade
Grade
Grade
-0.007
-0.011
2.487
2.245
0.336
0.094
2.144
2.140
2.813
2.535
0.363
0.085
-4 Speed
-4 Speed
-4 Speed
Grade
Grade
Grade
-0.021
-0.025
2.848
2.570
0.373
0.095
2.454
2.450
3.273
2.949
0.414
0.09
-5 Speed
-5 Speed
-5 Speed
Altera Corporation
Grade
Grade
Grade
-0.037
-0.042
3.309
2.985
0.424
2.848
2.843
0.1
April 2011
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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