EP2S30F672I4 Altera, EP2S30F672I4 Datasheet - Page 203

• Manufacturer Part Number: EP2S30F672I4
• Description: IC STRATIX II FPGA 30K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S30F672I4

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 500
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 500
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1899; EP2S30F672I4

Altera Corporation
April 2011
LVTTL
2.5-V LVTTL/CMOS
1.8-V LVTTL/CMOS
1.5-V LVTTL/CMOS
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 1 of 2)
Input I/O Standard
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Table 5–77
specifies the maximum output clock toggle rates at 0pF load.
specifies the derating factors for the output clock toggle rate for a non 0pF
load.
To calculate the output toggle rate for a non 0pF load, use this formula:
The toggle rate for a non 0pF load
For example, the output toggle rate at 0pF load for SSTL-18 Class II 20mA
I/O standard is 550 MHz on a -3 device clock output pin. The derating
factor is 94ps/pF. For a 10pF load the toggle rate is calculated as:
Column I/O Pins (MHz)
500
500
500
500
500
500
500
500
500
500
500
500
-3
= 1000 / (1000/ toggle rate at 0pF load + derating factor * load value
in pF /1000)
Tables 5–77
devices.
1000 / (1000/550 + 94 × 10 /1000) = 363 (MHz)
500
500
500
500
500
500
500
500
500
500
500
500
-4
specifies the maximum input clock toggle rates.
through
450
450
450
450
450
500
500
500
500
500
500
500
-5
5–79
500
500
500
500
500
500
500
500
500
500
500
500
-3
Row I/O Pins (MHz)
show the I/O toggle rates for Stratix II
500
500
500
500
500
500
500
500
500
500
500
500
-4
Stratix II Device Handbook, Volume 1
450
450
450
450
450
500
500
500
500
500
500
500
-5
DC & Switching Characteristics
Dedicated Clock Inputs
500
500
500
500
500
500
500
500
500
500
500
500
-3
(MHz)
Table 5–78
500
500
500
500
500
500
500
500
500
500
500
500
-4
Table 5–79
400
400
400
400
400
500
500
500
500
500
500
500
-5
5–67