EP2S60F672C4N Altera, EP2S60F672C4N Datasheet - Page 28

• Manufacturer Part Number: EP2S60F672C4N
• Description: IC STRATIX II FPGA 60K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F672C4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 492
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 492
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1913; EP2S60F672C4N

Adaptive Logic Modules
2–20
Stratix II Device Handbook, Volume 1
arithmetic chain runs vertically allowing fast horizontal connections to
TriMatrix memory and DSP blocks. A shared arithmetic chain can
continue as far as a full column.
Similar to the carry chains, the shared arithmetic chains are also top- or
bottom-half bypassable. This capability allows the shared arithmetic
chain to cascade through half of the ALMs in a LAB while leaving the
other half available for narrower fan-in functionality. Every other LAB
column is top-half bypassable, while the other LAB columns are bottom-
half bypassable.
See the
information on shared arithmetic chain interconnect.
Register Chain
In addition to the general routing outputs, the ALMs in an LAB have
register chain outputs. The register chain routing allows registers in the
same LAB to be cascaded together. The register chain interconnect allows
an LAB to use LUTs for a single combinational function and the registers
to be used for an unrelated shift register implementation. These resources
speed up connections between ALMs while saving local interconnect
resources (see
advantage of these resources to improve utilization and performance.
“MultiTrack Interconnect” on page 2–22
Figure
2–15). The Quartus II Compiler automatically takes
section for more
Altera Corporation
May 2007