EP2SGX60EF1152I4 Altera, EP2SGX60EF1152I4 Datasheet - Page 269

IC STRATIX II GX 60K 1152-FBGA

EP2SGX60EF1152I4

Manufacturer Part Number
EP2SGX60EF1152I4
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX60EF1152I4

Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2186

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX60EF1152I4
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX60EF1152I4
Manufacturer:
ALTERA
0
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
ALTERA
Quantity:
534
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
ALTERA
0
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
ALTERA
Quantity:
300
Part Number:
EP2SGX60EF1152I4N
0
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class I I
1.5-V HSTL Class I
1.5-V HSTL Class I I
1.8-V HSTL Class I
1.8-V HSTL Class II
Differential SSTL-2
Class I
Differential SSTL-2
Class II
Differential SSTL-18
Class I
PCI
PCI-X
Table 4–88. Stratix II GX Maximum Input Clock Rate for Column I/O Pins (Part 1 of 2)
I/O Standard
-3 Speed Grade
To calculate the output toggle rate for a non 0 pF load, use this formula:
The toggle rate for a non 0 pF load
For example, the output toggle rate at 0 pF load for SSTL-18 Class II
20 mA I/O standard is 550 MHz on a -3 device clock output pin. The
derating factor is 94 ps/pF. For a 10 pF load the toggle rate is calculated
as:
Table 4–88
device column pins.
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
= 1,000 / (1,000/ toggle rate at 0 pF load + derating factor × load
value in pF /1,000)
1,000 / (1,000/550 + 94 × 10 /1,000) = 363 (MHz)
shows the maximum input clock toggle rates for Stratix II GX
-4 Speed Grade
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
-5 Speed Grade
450
450
450
450
450
500
500
500
500
500
500
500
500
450
450
500
500
500
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz

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