EP3C16F256C7 Altera, EP3C16F256C7 Datasheet - Page 13

• Manufacturer Part Number: EP3C16F256C7
• Description: IC CYCLONE III FPGA 16K 256FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F256C7

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 168
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-2460

Early System Planning
© November 2008 Altera Corporation
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To know whether the input frequencies and output frequencies can be implemented
in one PLL, enter your settings when instantiating the altpll megafunction through
the Quartus II software.
To obtain the input and output clock frequency range specifications for the different
device speed grades, refer to the
Characteristics
Number of Clock Inputs
Cyclone III PLLs can have a maximum of two clock inputs, where only one clock
input functions at a time. You need two clock inputs for your PLL for applications
such as clock redundancy or dual clock domain. Clock redundancy application
ensures there is a back-up input clock in case the current clock is not present. A dual
clock application enables the PLL to change to another input clock frequency during
operation. This feature is called clock switchover.
Cyclone III devices have automatic and manual clock switchover. Automatic
switchover enables the PLL to change to another clock input after the current clock
input becomes unavailable. Manual clock switchover enables the user to control the
switch of the input clocks.
If you do not use the PLL for these applications, one clock input is sufficient.
You can enable the clock switchover feature from the altpll megafunction.
Number of Clock Outputs
Cyclone III PLLs can have a maximum of five clock outputs (c0-c4). You can connect
the c0 clock output to the dedicated external clock output pin (recommended as this
minimizes the clock jitter), normal user I/O or dedicated global clock network. The
c1, c2, c3, and c4 clock outputs can be connected to the user I/O pins or dedicated
global clock networks.
Clock Input and Output I/O Standard
Dedicated clock input pins can support all I/O standards supported by the
Cyclone III device, except PPDS, RSDS, and mini-LVDS. Dedicated external clock
output pins can support all I/O standards supported by the Cyclone III device.
For more information about the I/O standard support, refer to the
I/O Features
PLL Design
After defining the requirements, these are the items that you must consider while
designing the PLL according to your application.
Selecting the Right Compensation Mode
Table 5
shows the four compensation modes that Cyclone III devices support.
chapter in volume 1 of the Cyclone III Device Handbook.
chapter in volume 2 of the Cyclone III Device Handbook
Cyclone III Device Datasheet: DC and Switching
Cyclone III Device
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