EP3C16F256C7 Altera, EP3C16F256C7 Datasheet - Page 48

• Manufacturer Part Number: EP3C16F256C7
• Description: IC CYCLONE III FPGA 16K 256FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F256C7

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 168
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-2460

Page 48
Verification
I/O Timing Analysis
Perform I/O analysis with the TimeQuest Timing Analyzer or Classic Timing
Analyzer to ensure that the Cyclone III device meets the timing requirement when
interfacing with external devices on the board. If you know the maximum or
minimum delay of a signal from a register of an external device to a specified input or
bidirectional pin on the Cyclone III device relative to a specified clock source, use the
Input Delay assignment.
For the registered output from the Cyclone III device, you can make the Output Delay
assignment for maximum or minimum delay of a signal from the registered output of
the Cyclone III device to the registered input of the external device, relative to a
specified clock source.
Skew Management
Skew refers to the arrival time difference of a signal at two different destinations. For
synchronous designs, we have clock and data skew due to the different path length of
the clock and data signals. The effect of the skew is more significant on high speed
signals, due to the short time period of the signals. Using the clock network for these
high speed signals results in lower clock and data skew.
Use the Quartus II Maximum Clock Arrival Skew assignment to specify the
maximum allowable clock arrival skew between a clock signal and various
destination registers. For data signals, use the Maximum Data Arrival Skew
assignment to specify the maximum allowable data arrival skew to various
destination registers or pins. When these assignments are used, the Quartus II
software determines the timing difference between the longest clock or data path, and
the shortest clock or data path so that the Fitter attempts to meet the requirement.
Area and Timing Optimization
Physical synthesis optimizations make placement-specific changes to the netlist that
improve results for a specific Altera device. You can specify Physical synthesis for
performance or Physical synthesis for fitting options under the Fitter Settings, as in
Figure
9. These options typically increase compilation time significantly but can
provide significant improvements to the compilation result. If you turn on these
options, ensure that they do improve the results for your design.
© November 2008 Altera Corporation