EP3C16F256C7 Altera, EP3C16F256C7 Datasheet - Page 29

• Manufacturer Part Number: EP3C16F256C7
• Description: IC CYCLONE III FPGA 16K 256FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F256C7

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 168
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-2460

Design and Compilation
© November 2008 Altera Corporation
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For the specific HDL coding examples and recommendations, refer to the
Recommended HDL Coding Styles
to your synthesis tool's documentation for any additional tool-specific guidelines. In
the Quartus II software, you can use the HDL examples in the Language Templates
available from the right-click menu in the text editor.
The Quartus II software is able to generate the symbol or HDL files for the
megafunctions you create and allows you to integrate the megafunction into your
design, regardless of the design entry method. You can also generate the symbol file
for certain blocks in your design written in HDL. With that, your design can have a
mixture of HDL and schematic entry. You can infer certain device resources, for
example the memory, through HDL as well.
Selecting a Synthesis Tool
The Quartus II software can synthesize design entries in Verilog HDL, VHDL, Altera
hardware description language (AHDL) and schematics. You can also use third-party
EDA synthesis tools to synthesize your Verilog or VHDL design, and then use the
Quartus II software to perform the placement and routing based on the generated
netlist. Specify the third-party synthesis tool in the New Project Wizard or the EDA
Tools Settings page of the Settings dialog box to use the correct Library Mapping File
for your synthesis netlist.
Your synthesis tool might offer the capability to create a Quartus II project and pass
constraints such as the EDA tool setting, device selection, and timing requirements
that you specified in your synthesis project. You can use this capability to save time
when setting up your Quartus II project for placement and routing.
Altera recommends using the most recent version of the third-party synthesis tools,
because tool vendors are continuously adding new features, fixing tool issues, and
enhancing performance for Altera devices. The EDA tools that can generate the netlist
for the Quartus II Fitter include Synplicity Synplify and SynplifyPro software,
Synopsys Design Compiler, and Mentor Graphics
and LeonardoSpectrum
netlist file in either EDIF Input File (.edf) or Verilog Quartus Mapped (.vqm) format.
For more information on the supported synthesis tools, refer to the appropriate
chapter in
Notes list the version of each synthesis tool that is officially supported by that version
of the Quartus II software.
SOPC Builder
The System-on-a-Programmable-Chip (SOPC) Builder system generation tool is
useful for creating systems based on processors, peripherals, and memories. SOPC
Builder allows you to build your SOPC in less time as you do not need to create the
designs for all the components in your system. The SOPC system can be a standalone
system, or you can integrate the SOPC system into your custom logic design. The
SOPC Builder comes together with the Quartus II software.
For more information about the SOPC Builder and how to build your SOPC system
with the SOPC Builder, refer to the Altera website at
www.altera.com/products/software/products/sopc/sop-index.html
SOPC Builder
Synthesis
of the Quartus II Handbook.
in volume 1 of the Quartus II Handbook. The Quartus II Release
™
software. The EDA tools normally generate the design
chapter in volume 1 of the Quartus II Handbook. Refer
®
Precision RTL Synthesis software,
or
Volume 4:
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