EP3C25F324I7N Altera, EP3C25F324I7N Datasheet - Page 3

• Manufacturer Part Number: EP3C25F324I7N
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7N

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2544

Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Features
Table 1–1. Cyclone III Device Family Features
© December 2009 Altera Corporation
Cyclone III LS
Cyclone III
Family
EP3CLS100
EP3CLS150
EP3CLS200
EP3CLS70
EP3C120
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
Device
EP3C5
■
■
Cyclone III device family supports vertical migration that allows you to migrate your
device to other devices with the same dedicated pins, configuration pins, and power
pins for a given package-across device densities. This allows you to optimize device
density and cost as your design evolves.
Table 1–1
Wide collection of pre-built and verified IP cores from Altera and Altera
Megafunction Partners Program (AMPP) partners
Supports high-speed external memory interfaces such as DDR, DDR2,
SDR SDRAM, and QDRII SRAM
■
Elements
119,088
100,448
150,848
198,464
10,320
15,408
24,624
39,600
55,856
81,264
70,208
Auto-calibrating PHY feature eases the timing closure process and eliminates
variations with PVT for DDR, DDR2, and QDRII SRAM interfaces
Logic
5,136
lists Cyclone III device family features.
M9K Blocks
Number of
126
260
305
432
333
483
666
891
46
46
56
66
Total RAM
1,161,216
2,396,160
2,810,880
3,981,312
3,068,928
4,451,328
6,137,856
8,211,456
423,936
423,936
516,096
608,256
Bits
Multipliers
18 x 18
126
156
244
288
200
276
320
396
23
23
56
66
PLLs
2
2
4
4
4
4
4
4
4
4
4
4
Cyclone III Device Handbook, Volume 1
Global Clock
Networks
10
10
20
20
20
20
20
20
20
20
20
20
Maximum
User I/Os
182
182
346
215
535
377
429
531
413
413
413
413
1–3