EP4CE40F29I7N Altera, EP4CE40F29I7N Datasheet - Page 10
EP4CE40F29I7N
Manufacturer Part Number
EP4CE40F29I7N
Description
IC CYCLONE IV FPGA 40K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE40F29I7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1134000
Number Of I /o
532
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
39600
Logic Cells
39600
Ram Bits
1161216
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE40F29I7N
Manufacturer:
NXP
Quantity:
1 200
Company:
Part Number:
EP4CE40F29I7N
Manufacturer:
ALTERA
Quantity:
672
1–10
Configuration
Cyclone IV Device Handbook, Volume 1
f
f
f
f
For more information, refer to the
chapter.
Cyclone IV devices use SRAM cells to store configuration data. Configuration data is
downloaded to the Cyclone IV device each time the device powers up. Low-cost
configuration options include the Altera EPCS family serial flash devices and
commodity parallel flash configuration options. These options provide the flexibility
for general-purpose applications and the ability to meet specific configuration and
wake-up time requirements of the applications.
Table 1–9
Table 1–9. Configuration Schemes for Cyclone IV Device Family
IEEE 1149.6 (AC JTAG) is supported on all transceiver I/O pins. All other pins
support IEEE 1149.1 (JTAG) for boundary scan testing.
For more information, refer to the
chapter.
For Cyclone IV GX devices to meet the PCIe 100 ms wake-up time requirement, you
must use passive serial (PS) configuration mode for the EP4CGX15/22/30 devices
and use fast passive parallel (FPP) configuration mode for the EP4CGX30F484 and
EP4CGX50/75/110/150 devices.
For more information, refer to the
Cyclone IV Devices
The cyclical redundancy check (CRC) error detection feature during user mode is
supported in all Cyclone IV GX devices. For Cyclone IV E devices, this feature is only
supported for the devices with the core voltage of 1.2 V.
For more information about CRC error detection, refer to the
Cyclone IV Devices
Cyclone IV GX
Cyclone IV E
Note to
(1) The FPP configuration scheme is only supported by the EP4CGX30F484 and EP4CGX50/75/110/150 devices.
Table
lists which configuration schemes are supported by Cyclone IV devices.
1–9:
Devices
chapter.
chapter.
External Memory Interfaces in Cyclone IV Devices
JTAG Boundary-Scan Testing for Cyclone IV Devices
Configuration and Remote System Upgrades in
Supported Configuration Scheme
Chapter 1: Cyclone IV FPGA Device Family Overview
AS, PS, JTAG, and FPP
AS, AP, PS, FPP, and JTAG
© December 2010 Altera Corporation
Cyclone IV Device Family Architecture
SEU Mitigation in
(1)