EPF10K30ETI144-2 Altera, EPF10K30ETI144-2 Datasheet - Page 60

• Manufacturer Part Number: EPF10K30ETI144-2
• Description: IC FLEX 10KE FPGA 30K 144-TQFP
• Manufacturer: Altera
• Series: FLEX-10KE®r

Specifications of EPF10K30ETI144-2

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 216
• Total Ram Bits: 24576
• Number Of I /o: 102
• Number Of Gates: 119000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-TQFP, 144-VQFP
• Family Name: FLEX 10KE
• Number Of Usable Gates: 30000
• Number Of Logic Blocks/elements: 1728
• # Registers: 102
• # I/os (max): 102
• Frequency (max): 200MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 1728
• Ram Bits: 24576
• Device System Gates: 119000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1944; EPF10K30ETI144-2

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
60
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DIN2IOE
DIN2LE
DCLK2IOE
DCLK2LE
DIN2DATA
SAMELAB
SAMEROW
SAMECOLUMN
DIFFROW
TWOROWS
LEPERIPH
LABCARRY
LABCASC
DRR
INSU
INH
OUTCO
PCISU
PCIH
PCICO
Table 28. Interconnect Timing Microparameters
Table 29. External Timing Parameters
Symbol
Symbol
Delay from dedicated input pin to IOE control input
Delay from dedicated input pin to LE or EAB control input
Delay from dedicated clock pin to IOE clock
Delay from dedicated clock pin to LE or EAB clock
Delay from dedicated input or clock to LE or EAB data
Routing delay for an LE driving another LE in the same LAB
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row
Routing delay for an LE driving an IOE in the same column
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row
Routing delay for a row IOE or EAB driving an LE or EAB in a different row
Routing delay for an LE driving a control signal of an IOE via the peripheral
control bus
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Register-to-register delay via four LEs, three row interconnects, and four local
interconnects
Setup time with global clock at IOE register
Hold time with global clock at IOE register
Clock-to-output delay with global clock at IOE register
Setup time with global clock for registers used in PCI designs
Hold time with global clock for registers used in PCI designs
Clock-to-output delay with global clock for registers used in PCI designs
Parameter
Parameter
Note (1)
Altera Corporation
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(8)
(9)
(9)
(9)
(9)
(9),(10)
(9)
,
,
Conditions
Conditions
(10)
(10)