EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 25

• Manufacturer Part Number: EP4CE55F29C8LN
• Description: IC CYCLONE IV FPGA 55K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F29C8LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 374
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–25. PLL Specifications for Cyclone IV Devices
Table 1–26. Embedded Multiplier Specifications for Cyclone IV Devices —Preliminary
Table 1–27. Memory Block Performance Specifications for Cyclone IV Devices —Preliminary
© December 2010 Altera Corporation
t
f
t
Notes to
(1) This table is applicable for general purpose PLLs and multipurpose PLLs.
(2) You must connect V
(3) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(4) The V
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less than 200 ps.
(6) Peak-to-peak jitter with a probability level of 10
(7) With 100-MHz scanclk frequency.
(8) The cascaded PLLs specification is applicable only with the following conditions:
■
■
(9) PLL cascading is not supported for transceiver applications.
9 × 9-bit multiplier
18 × 18-bit multiplier
M9K Block
CONFIGPLL
SCANCLK
CASC_OUTJITTER_PERIOD_DEDCLK
Memory
Upstream PLL—0.59 MHz  Upstream PLL bandwidth < 1 MHz
Downstream PLL—Downstream PLL bandwidth > 2 MHz
counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f
intrinsic jitter of the PLL when an input jitter of 30 ps is applied.
Table
CO
Mode
Symbol
frequency reported by the Quartus II software in the PLL Summary section of the compilation report takes into consideration the V
1–25:
FIFO 256 × 36
Single-port 256 × 36
Simple dual-port 256 × 36 CLK
True dual port 512 × 18 single CLK
(8),
CCD_PLL
Embedded Multiplier Specifications
Table 1–26
Memory Block Specifications
Table 1–27
(9)
to V
Number of Multipliers
CCINT
Mode
Time required to reconfigure scan chains for PLLs
scanclk frequency
Period jitter for dedicated clock output in cascaded
PLLs (F
Period jitter for dedicated clock output in cascaded
PLLs (F
Resources Used
through the decoupling capacitor and ferrite bead.
lists the embedded multiplier specifications for Cyclone IV devices.
lists the M9K memory block specifications for Cyclone IV devices.
OUT
OUT
1
1
 100 MHz)
 100 MHz)
–12
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the
Parameter
Resources Used
(Note
LEs
47
0
0
0
340
287
C6
1),
Memory
M9K
(2)
1
1
1
1
C7, I7, A7
(Part 2 of 2)—Preliminary
300
250
315
315
315
315
C6
Performance
C7, I7, A7
260
200
C8
274
274
274
274
Performance
Min
—
—
—
—
Cyclone IV Device Handbook, Volume 3
C8L, I8L
238
238
238
238
C8
VCO
240
185
specification.
3.5
C8L, I8L
Typ
—
—
—
200
200
200
200
(7)
C9L
175
135
Max
42.5
C9L
157
157
157
157
100
425
—
MHz
MHz
Unit
MHz
MHz
MHz
MHz
Unit
SCANCLK
CO
1–25
post-scale
cycles
MHz
Unit
mUI
ps