EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 35

• Manufacturer Part Number: EP4CE55F29C8LN
• Description: IC CYCLONE IV FPGA 55K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F29C8LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 374
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–42. IOE Programmable Delay on Column Pins for Cyclone IV E 1.2 V Core Voltage Devices
—Preliminary
Table 1–43. IOE Programmable Delay on Row Pins for Cyclone IV E 1.2 V Core Voltage Devices
© December 2010 Altera Corporation
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output
register to output pin
Input delay from
dual-purpose clock pin
to fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output
register to output pin
Input delay from
dual-purpose clock pin
to fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Parameter
Parameter
Table
Table
1–42:
1–43:
Table 1–42
core voltage devices.
Pad to I/O
dataout to
core
Pad to I/O
input register
I/O output
register to
pad
Pad to global
clock
network
Pad to I/O
dataout to
core
Pad to I/O
input register
I/O output
register to
pad
Pad to global
clock
network
Affected
Affected
Paths
Paths
and
Table 1–43
Number
Number
Setting
Setting
12
12
of
of
7
8
2
7
8
2
Offset
Offset
Min
Min
list the IOE programmable delay for Cyclone IV E 1.2 V
0
0
0
0
0
0
0
0
1.314 1.211 1.211 2.177 2.340 2.433 2.388 2.508
1.307 1.203 1.203
0.437 0.402 0.402 0.747 0.820 0.880 0.834 0.873
0.693 0.665 0.665 1.200 1.379 1.532 1.393 1.441
1.314 1.209 1.209 2.201 2.386 2.510 2.429 2.548
1.312 1.207 1.207 2.202 2.402 2.558 2.447 2.557
0.458 0.419 0.419 0.783 0.861 0.924 0.875 0.915
0.686 0.657 0.657 1.185 1.360 1.506 1.376 1.422
C6
C6
Fast Corner
Fast Corner
I7
I7
A7
A7
2.19
Max Offset
Max Offset
C6
C6
Cyclone IV Device Handbook, Volume 3
2.387 2.540 2.430 2.545
C7
C7
(Note
Slow Corner
Slow Corner
(Note
1), (2)—Preliminary
C8
C8
1),
(2)
I7
I7
1–35
A7
A7
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns