EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 33

• Manufacturer Part Number: EP4CE55F29C8LN
• Description: IC CYCLONE IV FPGA 55K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F29C8LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 374
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–38. Duty Cycle Distortion on Cyclone IV Devices I/O Pins
© December 2010 Altera Corporation
Output Duty Cycle
Notes to
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and IOE driving the dedicated and general
(2) Cyclone IV devices meet the specified duty cycle distortion at the maximum output toggle rate for each combination of I/O standard and current
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
purpose I/O pins.
strength.
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table
Symbol
f
1–38:
External Memory Interface Specifications
The external memory interfaces for Cyclone IV devices are auto-calibrating and easy
to implement.
For more information about the supported maximum clock rate, device and pin
planning, IP implementation, and device termination, refer to
Performance Specifications
Table 1–37
Table 1–37. Memory Output Clock Jitter Specifications for Cyclone IV Devices
Duty Cycle Distortion Specifications
Table 1–38
OCT Calibration Timing Specification
Table 1–39
power-up for Cyclone IV devices.
Table 1–39. Timing Specification for Series OCT with Calibration at Device Power-Up for Cyclone IV
Devices
—Preliminary
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Notes to
(1) Memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL
t
Note to
(1) OCT calibration takes place after device configuration and before entering user mode.
OCTCAL
standard.
output routed on a global clock (GCLK) network.
Table
Table
(Note
Min
45
Symbol
lists the memory output clock jitter specifications for Cyclone IV devices.
lists the worst case duty cycle distortion for Cyclone IV devices.
lists the duration of calibration for series OCT with calibration at device
1–39:
Parameter
1–37:
1)—Preliminary
C6
Max
55
of the External Memory Interface Handbook.
Min
Duration of series OCT with
calibration at device power-up
45
C7, I7
Max
55
(Note
Description
Symbol
t
t
t
JIT(duty)
JIT(per)
JIT(cc)
1),
Min
45
C8, I8L, A7
(2),
(3)—Preliminary
Max
–125
–200
–150
55
Min
Cyclone IV Device Handbook, Volume 3
Min
45
Section III: System
Maximum
Max
C9L
125
200
150
20
(Note
Max
55
1),
(2)
Unit
ps
ps
ps
Unit
Units
%
µs
1–33