EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet
EP4CE55F23C7
Specifications of EP4CE55F23C7
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EP4CE55F23C7 Summary of contents
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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www ...
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... The EP4CGX15 and EP4CGX30 (except for the F484 package) devices are considered HBM Class 0 per JEDEC standard 22-A114. Altera recommends handling the ESD-sensitive devices using the ESD control methods as stated in ANSI/ESD S20.20 or IEC61340-5-1. ...
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... The receiver CDR is able to track the incoming data with synchronous SSC modulation for the PCI Express If you are considering a custom protocol design that requires SSC modulation in a Basic mode configuration, Altera recommends designing with synchronous SSC modulation. SATA CDR PPM Tolerance ...
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... Workaround A workaround is being implemented in the ALTREMOTE_UPDATE megafunction and will be available in the future Quartus questions, contact Altera Technical Support at www.altera.com/support. Pin Connection Guidelines Update for Transceiver Applications that Run at ≥ 2.97 Gbps Data Rate You may not meet the protocol jitter specification or may have a higher bit error rate (BER) if you do not use the following guidelines. If your transceiver applications run at ≥ ...
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... Table 3. Reference Clock Pins and the Associated I/O Pins to be Grounded for ≥ 2.97 Gbps Transceiver Applications (Part Reference Package Bank Clock 3B REFCLK[1..0] 8B REFCLK[5..4] F27 3A (2), REFCLK2 8A (3), REFCLK3 March 2011 Altera Corporation Reference I/O Pins to Ground Clock Pins AC6 (CRC_ERROR) T9 AB7 (INIT_DONE) T10 AC7 (nCEO) (1) U9 AC5 U10 AD4 AB5 ...
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... DQ4B in × 8 groups ■ DQ5B in × 8/× 9 groups ■ DQ4B in × 16/× 18 ■ groups DQ2B in × 32/× 36 ■ groups If you use a DDR system, DQ5T in × 8/× 9, × 16/× 18, and × 32/× 36 groups will not be supported. (8) March 2011 Altera Corporation ...
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... PPM threshold values exceed the receiver CDR PPM tolerance between the upstream transmitter reference clock and the local receiver reference clock. March 2011 Altera Corporation Software Enforcement Plan Follow the guidelines documented in this errata sheet as the Quartus II software does not enforce these guidelines. ...
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... For a receiver design that has the ±500 PPM or ±1000 PPM options selected in the Programmable PPM Detector feature, Altera recommends evaluating the system operation with different options, ranging between ±62.5 PPM and ±300 PPM. To change the Programmable PPM Detector option, regenerate and recompile the ALTGX MegaWizard Plug-In Manager design file with the supported options ...
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... IP MegaWizard Plug-In Manager is populated accurately and the board trace models representative of the relevant system are correctly entered in the Pin Planner. March 2011 Altera Corporation Table 5 lists the current specification. Device ...
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... Cascading for Transceiver Applications is not Supported” ■ “Removal of ±500 PPM and ±1000 PPM Options for Programmable PPM ■ Detector in ALTGX MegaWizard Plug-In Manager” “External Memory Specification for DDR2 SDRAM” ■ Initial release. Document Revision History March 2011 Altera Corporation ...