EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet
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... Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.5 Cyclone IV Device Handbook, Volume 1 ...
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... Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera as- sumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...
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... Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Additional Information About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-xi How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-xi Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-xi Section I. Device Core Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1 Chapter 1. Cyclone IV FPGA Device Family Overview Cyclone IV Device Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Package Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Cyclone IV Device Family Speed Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Cyclone IV Device Family Architecture ...
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... Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Zero Delay Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Deterministic Latency Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 Clock Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 Post-Scale Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 Programmable Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 PLL Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 Cyclone IV Device Handbook, Volume 1 Contents © December 2010 Altera Corporation ...
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... High Speed Serial Interface (HSSI) Input Reference Clock Support . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 LVDS I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Designing with LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 BLVDS I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 Designing with BLVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 © December 2010 Altera Corporation v Cyclone IV Device Handbook, Volume 1 ...
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... Programming Serial Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Cyclone IV Device Handbook, Volume 1 Contents © December 2010 Altera Corporation ...
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... Accessing Error Detection Block Through User Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Recovering from CRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Chapter 10. JTAG Boundary-Scan Testing for Cyclone IV Devices IEEE Std. 1149.6 Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 © December 2010 Altera Corporation vii Cyclone IV Device Handbook, Volume 1 ...
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... External Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Hot-Socketing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Devices Driven Before Power- 11-2 I/O Pins Remain Tri-stated During Power- 11-2 Hot-socketing Feature Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 Power-On Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 Cyclone IV Device Handbook, Volume 1 Contents © December 2010 Altera Corporation ...
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... Part Number: CYIV-51009-1.1 Chapter 10 JTAG Boundary-Scan Testing for Cyclone IV Devices Revised: Part Number: CYIV-51010-1.1 Chapter 11 Power Requirements for Cyclone IV Devices Revised: Part Number: CYIV-51011-1.2 © December 2010 Altera Corporation Cyclone IV Device Handbook, Volume December 2010 November 2009 November 2009 February 2010 December 2010 ...
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... Cyclone IV Device Handbook, Volume 1 Chapter Revision Dates © December 2010 Altera Corporation ...
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... Technical support Technical training Non-technical support (General) (Software Licensing) Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Bold Type with Initial Capital ...
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... A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. A warning calls attention to a condition or possible situation that can cause you injury. The angled arrow instructs you to press Enter. The feet direct you to more information about a particular topic. Additional Information © December 2010 Altera Corporation ...
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... Revision History Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. © December 2010 Altera Corporation Section I. Device Core ® IV Cyclone IV Device Handbook, Volume 1 ...
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... Up to 360 18 × 18 multipliers for DSP processing intensive applications ■ Protocol bridging applications for under 1.5 W total power ■ © December 2010 Altera Corporation 1. Cyclone IV FPGA Device Family ® IV FPGA device family extends the Cyclone FPGA series Power Requirements for Cyclone IV chapter ...
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... V-by-One (up to 3.0 Gbps) ■ DisplayPort (2.7 Gbps) ■ Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps) ■ OBSAI (up to 3.072 Gbps) ■ Cyclone IV Device Handbook, Volume 1 Chapter 1: Cyclone IV FPGA Device Family Overview Cyclone IV Device Family Features © December 2010 Altera Corporation ...
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... The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the pin count. © December 2010 Altera Corporation 15,408 22,320 28,848 ...
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... Device Resources 73,920 109,424 149,760 4,158 5,490 6,480 198 280 360 4 (4) 4 (4) 4 (4) 4 (5) 4 ( 3.125 3.125 3.125 (8) 11 (8) 11 (8) 310 475 475 Clock Networks and PLLs in © December 2010 Altera Corporation ...
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Package Matrix Table 1–3 lists Cyclone IV E device package offerings. Table 1–3. Package Offerings for the Cyclone IV E Device Family Package E144 M164 Size (mm) 22 × × 8 Pitch (mm) 0.5 0.5 Device User I/O ...
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Table 1–4 lists Cyclone IV GX device package offerings, including I/O and transceiver counts. Table 1–4. Package Offerings for the Cyclone IV GX Device Family Package N148 F169 Size (mm) 11 × × 14 Pitch (mm) 0.5 LVDS ...
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... Notes to Table 1–6 (1) C8L, C9L, and I8L speed grades are applicable for the 1.0-V core voltage. (2) C6, C7, C8, I7, and A7 speed grades are applicable for the 1.2-V core voltage. © December 2010 Altera Corporation F169 F324 F484 — — C6, C7, C8, I7 — ...
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... The multiplier architecture in Cyclone IV devices is the same as in the existing Cyclone series devices. The embedded multiplier blocks can implement an 18 × two 9 × 9 multipliers in a single block. Altera offers a complete suite of DSP IP including finite impulse response (FIR), fast Fourier transform (FFT), and numerically controlled oscillator (NCO) functions for use with the multiplier blocks ...
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... Interfaces may span two or more sides of the device to allow more flexible board design. The Altera interface solution consists of a PHY interface and a memory controller. Altera supplies the PHY IP and you can use it in conjunction with your own custom memory controller or an Altera-provided memory controller ...
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... Cyclone IV devices use SRAM cells to store configuration data. Configuration data is downloaded to the Cyclone IV device each time the device powers up. Low-cost configuration options include the Altera EPCS family serial flash devices and commodity parallel flash configuration options. These options provide the flexibility for general-purpose applications and the ability to meet specific configuration and wake-up time requirements of the applications ...
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... You can configure the block with the Quartus II software’s PCI Express Compiler, which guides you through the process step by step. f For more information, refer to the © December 2010 Altera Corporation Transmitter Channel PCS TX Phase Compensation Byte Serializer ...
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... I: Industrial temperature (t Package 148 pins 14 = 169 pins 19 = 324 pins 23 = 484 pins 27 = 672 pins 31 = 896 pins © December 2010 Altera Corporation Reference and Ordering Information Optional Suffix Indicates specific device shipment method ES: Engineering sample N: Lead-free devices Speed Grade with 6 being the fastest = 0° ...
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... Table 1–10. Document Revision History Date Version December 2010 1.4 July 2010 1.3 March 2010 1.2 February 2010 1.1 November 2009 1.0 © December 2010 Altera Corporation EP4CE Package 8 = 164 pins 17 = 256 pins 22 = 144 pins 23 = 484 pins 29 = 780 pins Changes Made Updated for the Quartus II software version 10.1 release. ■ ...
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... Cyclone IV Device Handbook, Volume 1 Chapter 1: Cyclone IV FPGA Device Family Overview Document Revision History © December 2010 Altera Corporation ...
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... The ability to drive the following interconnects: Local ■ Row ■ Column ■ Register chain ■ Direct link ■ ■ Register packing support ■ Register feedback support © November 2009 Altera Corporation 2. Logic Elements and Logic Array Blocks in Cyclone IV Devices IV devices. ® Cyclone IV Device Handbook, Volume 1 ...
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... Clear Logic Reset (DEV_CLRn) Clock & Clock Enable Select labclk1 LE Carry-Out labclk2 labclkena1 labclkena2 2–6. Logic Elements Row, Column, And Direct Link D Q Routing ENA CLRN Row, Column, And Direct Link Routing Local Routing Register Chain Output © November 2009 Altera Corporation ...
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... Figure 2–2. Cyclone IV Device LEs in Normal Mode data1 data2 data3 cin (from cout of previous LE) data4 © November 2009 Altera Corporation II software automatically chooses the appropriate mode for common (Figure 2–2). The Quartus II Compiler automatically selects the Register Chain Connection sload sclear ...
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... LUT clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide) cout Register Bypass Register Feedback Logic Array Blocks Row, Column, and Q Direct link routing D Row, Column, and Direct link routing CLRN Local Routing Register Chain Output © November 2009 Altera Corporation ...
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... LAB through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive LEs through fast local and direct link interconnects. © November 2009 Altera Corporation Row Interconnect LAB Local Interconnect 2– ...
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... Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices PLL, or IOE output Direct link interconnect to left Local Interconnect LAB Control Signals Direct link interconnect from right LAB, M9K memory block, embedded multiplier, PLL, or IOE output Direct link interconnect to right LAB © November 2009 Altera Corporation ...
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... Quartus II software controls this pin. This chip-wide reset overrides all other control signals. Document Revision History Table 2–1 shows the revision history for this chapter. Table 2–1. Document Revision History Date Version November 2009 1.0 © November 2009 Altera Corporation 6 labclkena2 labclkena1 labclk1 labclk2 syncload Changes Made Initial release. 2–7 ...
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... Cyclone IV Device Handbook, Volume 1 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices Document Revision History © November 2009 Altera Corporation ...
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... Two clock-enable control signals for each port (port A and port B) Initialization file to pre-load memory content in RAM and ROM modes ■ © November 2009 Altera Corporation 3. Memory Blocks in Cyclone IV Devices Cyclone IV device designs. The embedded memory ® Cyclone IV Device Handbook, Volume 1 ...
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... Cyclone IV Chapter 3: Memory Blocks in Cyclone IV Devices Overview M9K Blocks 8192 × 1 4096 × 2 2048 × 4 1024 × 8 1024 × 9 512 × 16 512 × 18 256 × 32 256 × Outputs cleared Output latches only © November 2009 Altera Corporation ...
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... Table 3–2 lists the byte selection. Table 3–2. byteena for Cyclone IV Devices M9K Blocks byteena[3.. Note to Table 3–2: (1) Any combination of byte enables is possible. © November 2009 Altera Corporation (Note 1) Affected Bytes datain × 16 datain × 18 [7..0] [8..0] [15..8] [17..9] — — ...
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... FFCD doutn ABFF ABCD II software. The setting can either be the newly written data or ® “Single-Clock Mode” on page 3–15. Chapter 3: Memory Blocks in Cyclone IV Devices Overview (Note XXXX XX ABFF FFCD ABCD ABFF FFCD ABCD “Single-Port Mode” on © November 2009 Altera Corporation ...
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... Figure 3–3. Cyclone IV Devices Address Clock Enable During Read Cycle Waveform inclock rdaddress rden addressstall latched address (inside memory) q (synch) q (asynch) © November 2009 Altera Corporation address[0] address[0] register address[N] register address[N] addressstall clock Figure 3–4 show the address clock enable waveform during read and ...
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... Figure 3–5 shows the functional waveform for the asynchronous clear feature. Figure 3–5. Output Latch Asynchronous Clear Waveform clk aclr aclr at latch q Cyclone IV Device Handbook, Volume data Chapter 3: Memory Blocks in Cyclone IV Devices Overview “Memory Modes” © November 2009 Altera Corporation ...
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... Figure 3–6. Single-Port Memory Notes to Figure 3–6: (1) You can implement two single-port memory blocks in a single M9K block. (2) For more information, refer to © November 2009 Altera Corporation Plug-In Manager. ™ RAM Megafunction User shows the single-port memory configuration for Cyclone IV (Note ...
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... Figure 3–7. Cyclone IV Devices Single-Port Mode Timing Waveform clk_a wren_a rden_a address_a data_a q_a (old data) q_a (new data) Cyclone IV Device Handbook, Volume 1 Chapter 3: Memory Blocks in Cyclone IV Devices 3–15 a0(old data) a1(old data Memory Modes “Read-During-Write © November 2009 Altera Corporation ...
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... Care” data at that location or output “Old Data”. To choose the desired behavior, set the Read-During-Write option to either Don’t Care or Old Data in the RAM MegaWizard Plug-In Manager in the Quartus II software. For more information about this behavior, refer to © November 2009 Altera Corporation shows the simple dual-port memory configuration. data[ ] rdaddress[ ] ...
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... Chapter 3: Memory Blocks in Cyclone IV Devices Memory Modes din4 din5 din6 b2 b3 Figure 3–10 (Note 1) data_b[ ] address_b[] wren_b byteena_b[] clock_b clocken_b rden_b aclr_b q_b[] © November 2009 Altera Corporation ...
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... RAM block. Figure 3–11 shows true dual-port timing waveforms for the write operation at port A and read operation at port B. Registering the outputs of the RAM simply delays the q outputs by one clock cycle. © November 2009 Altera Corporation Write Port 8192 × 1 4096 × ...
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... If you need a larger shift register, you can cascade the M9K memory blocks. Cyclone IV Device Handbook, Volume dout0 dout1 dout2 din b0 b1 doutn dout0 Chapter 3: Memory Blocks in Cyclone IV Devices Memory Modes din4 din5 din6 dout3 din5 din4 b2 b3 dout2 dout1 © November 2009 Altera Corporation ...
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... Dual clock FIFO buffers are useful when transferring data from one clock domain to another clock domain. Cyclone IV devices M9K memory blocks do not support simultaneous read and write from an empty FIFO buffer. f For more information about FIFO buffers, refer to the Megafunction User © November 2009 Altera Corporation Guide. 3– Number of Taps ...
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... Each memory block port also supports independent clock enables for input and output registers. Cyclone IV Device Handbook, Volume 1 Chapter 3: Memory Blocks in Cyclone IV Devices Simple True Dual-Port Dual-Port Single-Port Mode Mode v — — Clocking Modes Mode ROM Mode FIFO Mode v — — — v — — © November 2009 Altera Corporation ...
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... There are two read-during-write data flows: same-port and mixed-port. shows the difference between these flows. Figure 3–13. Cyclone IV Devices Read-During-Write Data Flow write_a read_a © November 2009 Altera Corporation describe the functionality of the various RAM Port A data in Port A data out 3– ...
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... Figure 3–15. Same Port Read-During-Write: Old Data Mode clk_a wren_a rden_a address_a data_a q_a (asynch) Cyclone IV Device Handbook, Volume 1 Chapter 3: Memory Blocks in Cyclone IV Devices Figure 3–15 show sample functional waveforms of same port a0(old data) Design Considerations a1(old data) © November 2009 Altera Corporation ...
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... Because there is no conflict resolution circuitry built into M9K memory blocks, this results in unknown data being written to that location. Therefore, you must implement conflict-resolution logic external to the M9K memory block. © November 2009 Altera Corporation Guide ...
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... Table 3–6. Document Revision History Date Version November 2009 1.0 Cyclone IV Device Handbook, Volume 1 Chapter 3: Memory Blocks in Cyclone IV Devices RAM Megafunction User Guide Changes Made Initial release. Document Revision History and the © November 2009 Altera Corporation ...
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... II software cascades multiple embedded multiplier blocks together. There ® are no restrictions on the data width of the multiplier, but the greater the data width, the slower the multiplication process. Figure 4–1. Embedded Multipliers Arranged in Columns with Adjacent LABs © February 2010 Altera Corporation 4. Embedded Multipliers in Embedded Multiplier Column ...
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... Embedded Multiplier Block Overview × 9 × Multipliers (1) Multipliers ( 160 80 280 140 396 198 560 280 720 360 112 56 132 66 132 66 232 116 308 154 400 200 532 266 Memory Blocks in AN 306: Implementing Multipliers © February 2010 Altera Corporation ...
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... Depending on the data width or operational mode of the multiplier, a single embedded multiplier can perform one or two multiplications in parallel. For multiplier information, refer to “Operational Modes” on page © February 2010 Altera Corporation signa signb aclr clock ...
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... Cyclone IV Device Handbook, Volume 1 Chapter 4: Embedded Multipliers in Cyclone IV Devices Data A Logic Level signb Value Low Unsigned Low Signed High Unsigned High Signed Operational Modes Data B Result Logic Level Low Unsigned High Signed Low Signed High Signed © February 2010 Altera Corporation ...
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... Also, you can dynamically change the signa and signb signals and send these signals through dedicated input registers. 9-Bit Multipliers You can configure each embedded multiplier to support two 9 × 9 independent multipliers for input widths bits. © February 2010 Altera Corporation signa signb aclr clock ...
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... D Q ENA D Q CLRN ENA CLRN D Q ENA CLRN 9 × 9 Multiplier D Q ENA D Q CLRN ENA CLRN D Q ENA CLRN 9 × 9 Multiplier Embedded Multiplier Operational Modes Data Out 0 [17..0] Data Out 1 [17..0] © February 2010 Altera Corporation ...
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... Table 4–3. Document Revision History Date Version February 2010 1.1 November 2009 1.0 © February 2010 Altera Corporation Changes Made Added Cyclone IV E devices in Table 4–1 9.1 SP1 release. Initial release. 4–7 for the Quartus II software version ...
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... Cyclone IV Device Handbook, Volume 1 Chapter 4: Embedded Multipliers in Cyclone IV Devices Document Revision History © February 2010 Altera Corporation ...
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... For more information about the number of GCLK networks in each device density, refer to the Cyclone IV FPGA Device Family Overview © December 2010 Altera Corporation 5. Clock Networks and PLLs in IV device family. It includes details about the ® II software enables the PLLs and their features without external devices. ...
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... December 2010 Altera Corporation ...
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... EP4CGX30 information in this table refers to all EP4CGX30 packages except F484 package. (2) PLL_1 and PLL_2 are multipurpose PLLs while PLL_3 and PLL_4 are general purpose PLLs. (3) PLL_4 is only available in EP4CGX22 and EP4CGX30 devices in F324 package. (4) This pin applies to EP4CGX22 and EP4CGX30 devices. © December 2010 Altera Corporation GCLK Networks 3 4 ...
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Table 5–2. GCLK Network Connections for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Devices GCLK Network Clock Sources — — — — — — — — — — — — CLKIO4/DIFFCLK_2n — — — — — ...
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Table 5–2. GCLK Network Connections for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Devices GCLK Network Clock Sources — — — — — — — — — — — — — PLL_3_C1 — — — — ...
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Table 5–2. GCLK Network Connections for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Devices GCLK Network Clock Sources (3) — — — — — — — — — — — — — — — — — ...
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... PLL_3_C2 — — — — PLL_3_C3 — — — — PLL_3_C4 — — — — PLL_4_C0 — — — — PLL_4_C1 © December 2010 Altera Corporation (Note 1) (Part GCLK Networks — — — — — — — — — ...
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... December 2010 Altera Corporation — v ...
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... Dynamic GCLK clock source selection (not applicable for DPCLK, CDPCLK , and internal logic input) ■ GCLK network power down (dynamic enable and disable) © December 2010 Altera Corporation Guidelines. Description Dedicated clock input pins can drive clocks or global signals, such as synchronous and asynchronous clears, presets, or clock enables onto given GCLKs ...
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... Chapter 5: Clock Networks and PLLs in Cyclone IV Devices Internal Logic DPCLK PLL PLL ( for the PLL. IN ALTCLKCTRL Megafunction User Clock Networks Clock Control Block Enable/ Global Disable Clock Static Clock Select (3) Internal Logic (5) CLKSELECT[1..0] (2) Figure 5–1. Guide. © December 2010 Altera Corporation ...
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... The EP4CGX15 device has two DPCLK pins on three sides of the device: DPCLK2 and DPCLK5 on bottom side, DPCLK7 and DPCLK8 on the right side, DPCLK10 and DPCLK13 on the top side of device. (6) Dedicated clock pins can feed into this PLL. However, these paths are not fully compensated. © December 2010 Altera Corporation 5–3, and Figure 5–4 on page 5–13 DPCLK[11 ...
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... Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices DPCLK[17..15] DPCLK[14..12] CLKIO[11.. Clock Control Block (3) GCLK[29.. GCLK[29..0] Clock Control Block ( CLKIO[15..12] DPCLK[2..0] DPCLK[5..3] Clock Networks PLL_4 ( DPCLK[11..9] 3 Clock CLKIO[7..4] Control 4 Block (3) DPCLK[8.. (6) PLL_3 © December 2010 Altera Corporation ...
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... Four clock input pins ■ Ten PLL counter outputs (five from each adjacent PLLs) ■ Two, four, or six DPCLK pins from the top, bottom, and right sides of the device ■ Five signals from internal logic © December 2010 Altera Corporation DPCLK[11.10] DPCLK[9..8] CLK[11.. ...
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... Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices 5–10. 4 Clock Input Pins 10 PLL Outputs Clock (2) Control DPCLK (1) Block 5 Internal Logic Five or six clock control blocks on each side of the device Figure 5–1 on page Clock Networks GCLK 5–10. © December 2010 Altera Corporation ...
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... In addition, the PLL can remain locked independent of the clkena signals because the loop-related counters are not affected. Figure 5–7 shows how to implement the clkena signal with a single register. Figure 5–7. clkena Implementation © December 2010 Altera Corporation Clock Input Pins 5 PLL Outputs ...
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... The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during PLL resynchronization. Altera recommends using the clkena signals when switching the clock source to the PLLs or the GCLK. The recommended sequence is: 1. Disable the primary output clock by de-asserting the clkena signal. ...
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... Input clock switchover User mode reconfiguration Loss of lock detection PLL drives TX Serial Clock, TX Load Enable, and TX Parallel Clock VCO output drives RX clock data recovery (CDR) clock © December 2010 Altera Corporation Cyclone IV Device Family Overview General Purpose PLLs PLL_1 PLL_2 PLL_3 PLL_4 ...
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... Mode, Normal Mode, and Zero Delay Buffer Mode PLLs in Cyclone IV Devices Availability Multipurpose PLLs PLL_2 PLL_5 PLL_6 PLL_7 (4) (4) (1),(10) (1),(10) ( Availability 512 (1) 1 single-ended or 1 differential pair 4 single-ended or 2 differential pairs v (2) Through GCLK Down to 96-ps increments ( © December 2010 Altera Corporation PLL_8 (1) scale counters ...
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... For the general purpose PLL and multipurpose PLL counter outputs connectivity to the GCLKs, refer to page 5–4. (6) Only the CI output counter can drive the TX serial clock. (7) Only the C2 output counter can drive the TX load enable. (8) Only the C3 output counter can drive the TX parallel clock. © December 2010 Altera Corporation (Note 1) lock LOCK circuit 8 ÷ ...
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... Range VCOUNDR Detector no compensation; ZDB mode source-synchronous; normal mode specification specified in the Cyclone IV Device Datasheet VCO Cyclone IV PLL Hardware Overview ÷C0 GCLKs ÷C1 External clock output ÷C2 PLL output ÷C3 mux ÷C4 ÷M GCLK networks chapter. © December 2010 Altera Corporation ...
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... Cyclone IV PLLs can drive out to any regular I/O pin through the GCLK. You can also use the external clock output pins as GPIO pins if external PLL clocking is not required. © December 2010 Altera Corporation Figure 5–11, without going through the GCLK. Other ...
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... Chapter 5: Clock Networks and PLLs in Cyclone IV Devices Table 5–5 on page 5–17 Table 5–6 on page 5–18 for Cyclone IV E PLLs. Data pin PLL reference clock at input pin Data at register Clock at register Clock Feedback Modes for - Synchronous Mode © December 2010 Altera Corporation ...
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... Figure 5–13. Phase Relationship Between PLL Clocks in No Compensation Mode Notes to Figure 5–13: (1) Internal clocks fed by the PLL are phase (2) The PLL clock outputs can lead or lag the PLL input clocks. © December 2010 Altera Corporation Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port ...
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... Register Clock Port External PLL Clock Outputs Note to Figure 5–14: (1) The external clock output can lead or lag the PLL internal clock signals. Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices Phase Aligned (1) Clock Feedback Modes © December 2010 Altera Corporation ...
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... Common Public Radio Interface (CPRI) applications. In this mode, the PLL PFD feedback path compensates the latency uncertainty in Tx dataout and Tx clkout paths relative to the reference clock. © December 2010 Altera Corporation Phase Aligned PLL Reference Clock ...
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... ALTPLL megafunction. 1 Phase alignment between output counters is determined using the t specification. Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices (M/N). Each output port has a unique post-scale counter that IN Hardware Features PLL_PSERR © December 2010 Altera Corporation ...
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... For example, if the C0 counter is 10, steps of 5% are possible for duty cycle choices between 5 to 90%. Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks. © December 2010 Altera Corporation Figure 5–16. VCO Output ...
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... Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices Switchover Clock State Sense Machine clksw n Counter refclk muxout Hardware Features ALTPLL Megafunction clkbad0 clkbad1 activeclock clkswitch (provides manual switchover support) PFD fbclk © December 2010 Altera Corporation ...
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... Figure 5–18. Automatic Switchover Upon Clock Loss Detection Note to Figure 5–18: (1) Switchover is enabled on the falling edge of inclk0 or inclk1, depending on which clock is available. In this figure, switchover is enabled on the falling edge of inclk1. © December 2010 Altera Corporation inclk0 inclk1 (1) muxout clkbad0 clkbad1 activeclock 5– ...
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... Both inclk0 and inclk1 must be running when the clkswitch signal goes high to start a manual clock switchover event. Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices (1) inclk0 inclk1 muxout clkswitch activeclock clkbad0 clkbad1 Hardware Features © December 2010 Altera Corporation ...
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... VCO locks on to the secondary clock. After the VCO locks on to the secondary clock, some overshoot can occur (an over-frequency condition) in the VCO frequency. © December 2010 Altera Corporation Guide. shows how the VCO frequency gradually decreases when the primary 5– ...
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... This allows you to adjust the delay time with a fine resolution. Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices Primary Clock Stops Running Switchover Occurs Programmable Bandwidth Frequency Overshoot VCO Tracks Secondary Clock © December 2010 Altera Corporation ...
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... In this case, the two clocks are offset by 3 0° phase from the VCO but has the C value for the counter set to three. This creates a delay of two © December 2010 Altera Corporation shows the minimum delay time that you can insert using this method ...
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... PLLs, the source (upstream) PLL must have a low-bandwidth setting, while the destination (downstream) PLL must have a high-bandwidth setting. 1 PLL_6 and PLL7 have upstream cascading capability only. Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices t VCO PLL Cascading © December 2010 Altera Corporation ...
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... MHz. After shifting the last bit of data, asserting the configupdate signal for at least one scanclk clock cycle synchronously updates the PLL configuration bits with the data in the scan registers. © December 2010 Altera Corporation 5–35 ) delays in real time by ...
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... C counters, or the I 7. You can repeat steps Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices PFD LF/K/CP VCO /C2 /C1 / settings through 5 to reconfigure the PLL any number of times. © December 2010 Altera Corporation PLL Reconfiguration F VCO /M /N ...
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... The PLL implements this duty cycle by transitioning the output clock from high-to-low on the rising edge of the VCO output clock. However and 6 setting for the high and low count values, respectively, would produce an output clock with a 40–60% duty cycle. © December 2010 Altera Corporation 5–37 Dn (MSB) Dn_old ...
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... MSB bit for loop filter is the last bit shifted into the scan chain. Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices Number of Bits Counter Other count value is the first bit shifted into the scan chain. PLL Reconfiguration Total (2) 18 (2) 18 (2) 18 (2) 18 (2) 18 ( 144 © December 2010 Altera Corporation ...
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... You can reconfigure the charge pump and loop filter settings to update the PLL bandwidth in real time. charge pump current (I Cyclone IV devices. Table 5–8. Charge Pump Bit Control CP[ Table 5–9. Loop Filter Resistor Value Control (Part LFR[ © December 2010 Altera Corporation LF CP MSB LSB DATAOUT ...
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... Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices LFR[3] LFR[ LFC[ LSB PLL Reconfiguration Setting LFR[1] LFR[0] (Decimal Setting (Decimal Description MSB 1 (1) PLL counter bypassed 0 (1) PLL counter not bypassed © December 2010 Altera Corporation ...
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... December 2010 Altera Corporation Description Counter Select. Three bits decoded to select either the M or one of the C counters for phase adjustment. One address map to select all C counters. This signal is registered in the PLL on the rising edge of scanclk. Selects dynamic phase shift direction DOWN ...
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... Chapter 5: Clock Networks and PLLs in Cyclone IV Devices 1 through 4 as many times as required to get multiple phase or t requirements (with respect to the scanclk edges phaseupdown scanclk phasestep phasedone or t requirements (with respect to scanclk edges PLL Reconfiguration Figure 5–26, Guide. © December 2010 Altera Corporation ...
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... February 2010 2.0 ■ ■ ■ November 2009 1.0 Initial release. © December 2010 Altera Corporation Changes Made Updated for the Quartus II software version 10.1 release. Updated Figure 5–3 and Figure 5–10. Updated “GCLK Network Clock Source Generation”, and “ ...
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... Cyclone IV Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices Document Revision History © December 2010 Altera Corporation ...
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... Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. © December 2010 Altera Corporation Section II. I/O Interfaces IV device family I/O features and ® ...
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...
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... The I/O capabilities of Cyclone IV devices are driven by the diversification of I/O standards in many low-cost applications, and the significant increase in required I/O performance. Altera’s objective is to create a device that accommodates your key board design needs with ease and flexibility. The I/O flexibility of Cyclone IV devices is increased from the previous generation low-cost FPGAs by allowing all I/O standards to be selected on all I/O banks ...
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... ENA ACLR sclr/ /PRN preset D Q ENA ACLR /PRN Input Register Chapter 6: I/O Features in Cyclone IV Devices Cyclone IV I/O Elements V CCIO V CCIO Programmable Pull-Up Resistor Bus Hold Input Pin to Input Register Delay or Input Pin to Logic Array Delay © December 2010 Altera Corporation ...
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... I/O pin. This open-drain output enables the device to provide system-level control signals (for example, interrupt and write enable signals) that are asserted by multiple devices in your system. © December 2010 Altera Corporation shows the possible settings for I/O standards with current Table 6–2 on page 6–7 shows the possible slew rate option 6– ...
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... Each dual-purpose clock input pin provides a programmable delay to the global clock networks. Cyclone IV Device Handbook, Volume 1 Chapter 6: I/O Features in Cyclone IV Devices voltage level driven through the CCIO chapter. level of the output pin’s bank. CCIO © December 2010 Altera Corporation I/O Element Features ...
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... IOE registers. f For more information about the input and output pin delay settings, refer to the and Timing Optimization © December 2010 Altera Corporation Quartus II Logic Option Input delay from pin to internal cells Input delay from pin to input register Delay from output register to output pin Input delay from dual-purpose clock pin to fan-out destinations chapter in volume 2 of the Quartus II Handbook ...
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... LVTTL/LVCMOS ■ PCI ■ PCI-X If the input I/O standard is one of the listed standards, the PCI-clamp diode is enabled by default in the Quartus II software. Cyclone IV Device Handbook, Volume 1 Chapter 6: I/O Features in Cyclone IV Devices I/O Element Features © December 2010 Altera Corporation ...
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... HSTL-18 Class I 8,10,12 HSTL-18 Class II 16 HSTL-15 Class I 8,10,12 HSTL-15 Class II 16 HSTL-12 Class I 8,10,12 HSTL-12 Class II 14 © December 2010 Altera Corporation OCT, programmable current strength is not available OCT with S Calibration (1) Setting, Ohm () Setting, Ohm () Column Row Column ...
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... December 2010 Altera Corporation Slew PCI- Rate clamp Diode (6) Support — — — 0,1,2 — — — 0,1,2 — — — ...
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... OCT calibration block to dynamically adjust buffer impedance. 1 During calibration, the resistance of the RUP and RDN pins varies. © December 2010 Altera Corporation OCT with calibration in the top, bottom, and right I/O S OCT calibration circuit compares the total impedance of the I/O buffer Figure 6– ...
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... Chapter 6: I/O Features in Cyclone IV Devices OCT with Calibration Setup S Cyclone IV Device Family OCT with Calibration with RUP and RDN pins RUP OCT Calibration V CCIO Circuitry RDN OCT Support V CCIO External Calibration Resistor External Calibration Resistor GND © December 2010 Altera Corporation ...
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... Impedance matching is implemented using the capabilities of the output driver and is subject to a certain degree of variation, depending on the process, voltage, and temperature. f For more information about tolerance specification, refer to the Datasheet chapter. © December 2010 Altera Corporation = 50 ) for SSTL-2 and SSTL-18. S OCT Without Calibration S Cyclone IV Device Driver Series Termination ...
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... December 2010 Altera Corporation Pins — v — — — — — — — — — — ...
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... The 3.3-V LVTTL, 3.0-V LVTTL and LVCMOS, 2.5-V LVTTL and LVCMOS, 1.8-V LVTTL and LVCMOS, 1.5-V LVCMOS, 1.2-V LVCMOS, 3.0-V PCI, and PCI-X I/O standards do not specify a recommended termination scheme per the JEDEC standard © December 2010 Altera Corporation V Level (in V) CCIO ...
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... Termination Scheme for I/O Standards ) and a REF Figure 6–5 and Figure 6–6. HSTL Class Ω 50 Ω 50 Ω V REF Receiver Ω 50 Ω 50 Ω V REF Receiver SSTL Class Ω 50 Ω 25 Ω 50 Ω V REF Receiver Ω 50 Ω Ω REF Receiver © December 2010 Altera Corporation ...
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... On-Board 25 Ω Termination Transmitter Cyclone IV Device Family Series OCT Ω 50 OCT Transmitter Note to Figure 6–8: (1) Only Differential SSTL-2 I/O standard supports Class II output. © December 2010 Altera Corporation Figure 6–7 and Figure Ω 50 Ω Transmitter Receiver Cyclone IV Device 50 Ω Family Series OCT Ω ...
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... For more information about the transceiver channels supported, refer to Cyclone IV Device Handbook, Volume 1 Chapter 6: I/O Features in Cyclone IV Devices and Figure 6–11 on page Figure 6–10 on page 6–18 and Figure 6–11 on page I/O Banks Figure 6–9. Each device I/O 6–19. The Cyclone IV GX 6–19. © December 2010 Altera Corporation ...
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... The differential HSTL-12 I/O standard is only supported on clock input pins and PLL output clock pins. Differential HSTL-12 Class II is supported only in column I/O banks and 8. (7) BLVDS output uses two single-ended outputs with the second output programmed as inverted. BLVDS input uses true LVDS input buffer. © December 2010 Altera Corporation 1), (2) ...
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... I/O Bank I/O Bank 4 3A (10) VCCIO4 VCC_CLKIN3A Chapter 6: I/O Features in Cyclone IV Devices I/O Banks (Note 1), (2), (9) VCCIO6 I/O bank with calibration block I/O bank without calibration block Calibration block coverage VCCIO5 OCT without calibration and they S © December 2010 Altera Corporation ...
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... The dedicated clock input I/O banks 3A, 3B, 8A, and 8B can be used either for HSSI input reference clock pins or clock input pins. (11) Single-ended clock input support is available for dedicated clock input I/O banks 3B and 8B. © December 2010 Altera Corporation VCCIO8 VCC_CLKIN8A VCCIO7 ...
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Each Cyclone IV I/O bank has a VREF bus to accommodate voltage-referenced I/O standards. Each VREF pin is the reference source for its V group. If you use a V REF the appropriate voltage level. If you do not use ...
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... Cyclone IV Device Datasheet 1 The PCI clamping diode is enabled by default in the Quartus II software for input signals with bank V © December 2010 Altera Corporation 4CGX30 4CGX50 4CGX75 169- 324- 484- ...
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... You can use the Quartus II software to validate your pad and pin placement. Pad Placement Altera recommends that you create a Quartus II design, enter your device I/O assignments and compile your design to validate your pin placement. The Quartus II software checks your pin connections with respect to the I/O assignment and placement rules to ensure proper device operation ...
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... I/O banks using two single-ended output with the second output programmed as inverted, and an external resistor network. True input buffers for these I/O standards are supported on the top, bottom, and right I/O banks except for I/O bank 9. © December 2010 Altera Corporation Table 6–3 on page 6–12. Table 6–3 on page 6– ...
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... Three Resistors 1,2,5,6 Not Required All Three Resistors All Single Resistor All — All — All — All — All — All — Chapter 6: I/O Features in Cyclone IV Devices High-Speed I/O Interface Transmitter (TX) Receiver (RX — v — v — — © December 2010 Altera Corporation ...
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... The differential interface data serializers and deserializers (SERDES) are automatically constructed in the core logic elements (LEs) with the Quartus II software ALTLVDS megafunction. © December 2010 Altera Corporation External Resistor I/O Bank Location Network at ...
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Table 6–8 and Table 6–9 device family. Table 6–8. Cyclone IV E I/O and Differential Channel Count Device EP4CE6 EP4CE10 Numbers of Differential 144- 256- 256- 144- 256- 256- 144- EQPF UBGA FBGA EQPF UBGA FBGA EQPF Channels (1),(2) (3) ...
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... For more information about the CLKIN/REFCLK pin location, refer to page 6–19. The CLKIN/REFCLK pins are powered by dedicated V and V CC_CLKIN8B different power level requirements in the same bank for GPIO. © December 2010 Altera Corporation 4CGX30 4CGX50 169- 324- 484- 484- 672- ...
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... I/O Pin Type Column Row Supported I/O I/O I/O Banks Not Yes No 3A, 3B, 8A, 8B Not Yes No 3A, 3B, 8A, 8B Not Yes No 3A, 3B, 8A, 8B Not Yes No 3A, 3B, 8A, 8B Not Yes No 3A, 3B, 8A, 8B Not Yes No 3A, 3B, 8A, 8B chapter increased to 600 mV. The OD © December 2010 Altera Corporation ...
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... LVDS to multipoint configuration that supports bidirectional half-duplex communication. BLVDS differs from standard LVDS by providing a higher drive to achieve similar signal swings at the receiver while loaded with two terminations at both ends of the bus. © December 2010 Altera Corporation Cyclone IV Device txout + Cyclone IV ...
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... For more information about BLVDS interface support in Altera devices, refer to AN 522: Implementing Bus LVDS Interface in Supported Altera Device Cyclone IV Device Handbook, Volume 1 50 Ω ...
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... RSDS, mini-LVDS, or PPDS interface with a true output buffer. Figure 6–15. Cyclone IV Devices RSDS, Mini-LVDS, or PPDS Interface with True Output Buffer on the Right I/O Banks Cyclone IV Device True RSDS, Mini-LVDS, or PPDS Transmitter © December 2010 Altera Corporation chapter. RSDS, Mini-LVDS, or PPDS Receiver 50 Ω Ω ...
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... The resistor values chosen must satisfy Equation 6–1. Resistor Network 1 Altera recommends that you perform simulations using Cyclone IV devices IBIS models to validate that custom resistor values meet the RSDS, mini-LVDS, or PPDS requirements possible to use a single external resistor instead of using three resistors in the ...
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... AC-coupled termination scheme. The 50- resistors used at the receiver are external to the device. DC-coupled LVPECL is supported if the LVPECL output common mode voltage is in the Cyclone IV devices LVPECL input buffer specification (refer to © December 2010 Altera Corporation Single Resistor Network 50 Ω Ω ...
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... Figure 6–18. LVPECL AC-Coupled Termination Note to Figure 6–18: (1) The LVPECL AC-coupled termination is applicable only when an Altera FPGA transmitter is used. Figure 6–19 shows the LVPECL DC-coupled termination. Figure 6–19. LVPECL DC-Coupled Termination LVPECL Transmitter Note to Figure 6–19: (1) The LVPECL DC-coupled termination is applicable only when an Altera FPGA transmitter is used. ...
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... The amount of pre-emphasis needed depends on the amplification of the high-frequency components along the transmission line. You must adjust the setting to suit your designs, as pre-emphasis decreases the amplitude of the low-frequency component of the output signal. © December 2010 Altera Corporation to which termination resistors are connected. CCIO “Differential I/O Standard ...
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... TUI SW TCCS – – RSKM = --------------------------------------------- - 2 — Allowed input jitter on the input clock to the PLL that is tolerable while maintaining PLL lock. — Peak-to-peak output jitter from the PLL. High-Speed I/O Timing Overshoot V OD Undershoot Figure 6–21. © December 2010 Altera Corporation ...
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... The equation for the high-speed I/O timing budget is: Period TCCS RSKM For more information, refer to the © December 2010 Altera Corporation External Input Clock Time Unit Interval (TUI) Internal Clock TCCS RSKM Receiver Sampling Window (SW) Input Data (Note 1) 0.5 × TCCS ...
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... Do not route TTL clock signals to areas under or above the differential signals. Analyze system-level signals. ■ Cyclone IV Device Handbook, Volume 1 Chapter 6: I/O Features in Cyclone IV Devices supply, you must observe some CCIO “Pad Placement and DC Guidelines” on page © December 2010 Altera Corporation Design Guidelines 6–22. ...
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... MSB of your parallel data first. f For more details about designing your high-speed I/O systems interfaces using the ALTLVDS megafunction, refer to the Quartus II Handbook. © December 2010 Altera Corporation AN 224: High-Speed Board Layout Guidelines PCBs. ALTLVDS Megafunction User Guide Cyclone IV Device Handbook, Volume 1 6–39 ...
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... Updated Table 6–2, Table 6–3, and Table 6–10. Updated “I/O Banks” section. Added Figure 6–9. Updated Figure 6–10 and Figure 6–11. Added Table 6–4, Table 6–6, and Table 6–8. Chapter 6: I/O Features in Cyclone IV Devices Document Revision History © December 2010 Altera Corporation ...
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... Altera DDR2 or DDR SDRAM memory controllers, third-party controllers custom controller for unique application needs. Cyclone IV devices support QDR II interfaces electrically, but Altera does not supply controller or physical layer (PHY) megafunctions for QDR II interfaces. This chapter includes the following sections: ■ ...
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... CQ signal in QDR II SRAM interfaces. 1 Cyclone IV devices do not support differential strobe pins, which is an optional feature in the DDR2 SDRAM device. f When you use the Altera Memory Controller MegaCore instantiated for you. For more information about the memory interface data path, refer to the External Memory Interface 1 ALTMEMPHY is a self-calibrating megafunction, enhanced to simplify the implementation of the read-data path in different memory interfaces ...
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... Table 7–1. Cyclone IV GX Device DQS and DQ Bus Mode Support for Each Side of the Device Device Package 148-pin QFN EP4CGX15 169-pin FBGA 169-pin FBGA EP4CGX22 324-pin FBGA EP4CGX30 484-pin FBGA (4) 484-pin FBGA EP4CGX50 EP4CGX75 672-pin FBGA © December 2010 Altera Corporation Number Number Side ×8 ×9 Groups Groups Right 1 0 Top ( Bottom ...
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... Number Number Number ×16 ×18 ×32 ×36 Groups Groups Groups Groups 0 0 — — — — — — — — — — — — — — — — — — — — — — — — © December 2010 Altera Corporation ...
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... Table 7–2. Cyclone IV E Device DQS and DQ Bus Mode Support for Each Side of the Device Device Package 144-pin EQFP 164-pin MBGA EP4CE15 256-pin UBGA 256-pin FBGA 484-pin FBGA 144-pin EQFP EP4CE22 256-pin UBGA 256-pin FBGA © December 2010 Altera Corporation Number Number Side ×8 ×9 Groups Groups Left 0 0 Right 0 ...
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... Bottom 4 4 Top 4 4 Left 4 4 Right 4 4 Bottom 6 6 Top 6 6 webpage. Cyclone IV Devices Memory Interfaces Pin Support (Note 1) (Part Number Number Number Number ×16 ×18 ×32 ×36 Groups Groups Groups Groups Device Packaging © December 2010 Altera Corporation ...
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... QFP, 169-pin FBGA, and 324-pin FBGA. Figure 7–3 shows the location and numbering of the DQS, DQ, or CQ# pins in I/O banks of the Cyclone IV GX device in the 324-pin FBGA package only. © December 2010 Altera Corporation II software issues an error message group is not placed properly I/O Bank 8B I/O Bank 8 ...
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... FBGA Package I/O Bank 3 I/O Bank 3A I/O Bank 4 I/O Bank 9 I/O Bank 8 I/O Bank 8A I/O Bank 7 Cyclone IV GX Device 148-pin QFP and 169-pin FBGA Packages I/O Bank 3 I/O Bank 3A I/O Bank 4 DQS2R/CQ1R DQS0R/CQ0R DQS1R/CQ0R# DQS3R/CQ1R# DQS0R/CQ0R DQS1R/CQ0R# © December 2010 Altera Corporation ...
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... DQS2L/CQ3L DQS0L/CQ1L DQS1L/CQ1L# DQS3L/CQ3L# Note to Figure 7–5: (1) The DQS, CQ, or CQ# pin locations in this diagram apply to all packages in Cyclone IV E devices except devices in 144-pin EQFP. © December 2010 Altera Corporation (Note 1) I/O Bank 8 I/O Bank 7 DQS2R/CQ3R DQS0R/CQ1R Cyclone IV E Device DQS1R/CQ1R# DQS3R/CQ3R# ...
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... The preassigned DQ and DM pins are the preferred pins to use. Cyclone IV Device Handbook, Volume 1 Chapter 7: External Memory Interfaces in Cyclone IV Devices Cyclone IV Devices Memory Interfaces Pin Support I/O Bank 8 I/O Bank 7 DQS0R/CQ1R Cyclone IV E Devices in 144-pin EQFP and 164-pin MBGA DQS1R/CQ1R# I/O Bank 3 I/O Bank 4 © December 2010 Altera Corporation ...
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... DQ pins. f For more information about memory clock pin placement, refer to Pin, and Board Layout Guidelines © December 2010 Altera Corporation of the External Memory Interface Handbook. Cyclone IV Device Handbook, Volume 1 7–11 ...
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... DDR data present during the rising edge of the clock I captures the DDR data present during the falling edge of the clock I aligns the data before it is synchronized with the system clock I Cyclone IV Devices Memory Interfaces Features DQ Capture Clock PLL . I © December 2010 Altera Corporation ...
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... DQS write preamble time specification. f For more information about Cyclone IV IOE registers, refer to the I/O Features chapter. © December 2010 Altera Corporation DDR Output Enable Registers IOE Register Output Enable Register A ...
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... Cyclone IV Devices Memory Interfaces Features Delay Half a Clock Cycle Preamble register D input. OE OCT control block (one for each side). You can use each S chapter. External Memory Interface Handbook. chapter. (Note 1) Postamble D3 OCT) in both S for that CCIO Clock Networks and PLLs in © December 2010 Altera Corporation ...
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... February 2010 2.0 ■ ■ November 2009 1.0 Initial release. © December 2010 Altera Corporation Changes Made Updated for the Quartus II software version 10.1 release. Added Cyclone IV E new device package information. Updated Table 7–2. Minor text edits. Added Cyclone IV E devices information for the Quartus II software version 9.1 SP1 release. Updated Table 7– ...
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... Cyclone IV Device Handbook, Volume 1 Chapter 7: External Memory Interfaces in Cyclone IV Devices Document Revision History © December 2010 Altera Corporation ...
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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. © December 2010 Altera Corporation Section III. System Integration Cyclone IV Device Handbook, Volume 1 ...
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...
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... Configuration” on page 8–39 ■ “JTAG Configuration” on page 8–44 “Device Configuration Pins” on page 8–61 ■ © December 2010 Altera Corporation 8. Configuration and Remote System Upgrades in Cyclone IV Devices (“Configuration Data Decompression” on (“Remote System Upgrade” on page Cyclone IV Device Handbook, Volume 1 IV ® ...
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... In the Settings dialog box, click OK. Cyclone IV Device Handbook, Volume 1 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Configuration Method Decompression v (2) — — — — Configuration Remote System Upgrade ( v(3) — v(3) — — Table 8–8 on page 8–21. © December 2010 Altera Corporation ...
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... This section describes Cyclone IV device configuration requirement and includes the following topics: “Power-On Reset (POR) Circuit” on page 8–4 ■ ■ “Configuration File Size” on page 8–4 ■ “Power Up” on page 8–6 © December 2010 Altera Corporation Figure 8–1 Serial Data Uncompressed V CC Decompression 10 kΩ ...
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... I/O banks in which the CCINT CCA CCIO chapter. Device EP4CE6 EP4CE10 EP4CE15 EP4CE22 EP4CE30 EP4CE40 EP4CE55 EP4CE75 EP4CE115 Configuration CCINT Cyclone IV Device Power Data Size (bits) 2,944,088 2,944,088 4,086,848 5,748,552 9,534,304 9,534,304 14,889,560 19,965,752 28,571,696 © December 2010 Altera Corporation ...
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... The output resistance of the repeater buffers and the TDO path for all cases must fit the maximum overshoot equation shown in Equation 8–1. Note to Equation ( the transmission line impedance and R O © December 2010 Altera Corporation Device EP4CGX15 EP4CGX22 EP4CGX30 EP4CGX50 EP4CGX75 EP4CGX110 EP4CGX150 Table 8– ...
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... Mode” on page 8–7 ■ f For more information about the Altera to the Configuring Altera FPGAs Power Up If the device is powered up from the power-down state, V the I/O banks in which the configuration and JTAG pins reside) must be powered up to the appropriate level for the device to exit from POR ...
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... INIT_DONE pin is released and pulled high. This low-to-high transition signals that the device has entered user mode. In user mode, the user I/O pins function as assigned in your design and no longer have weak pull-up resistors. © December 2010 Altera Corporation 8–7 Cyclone IV Device Handbook, Volume 1 ...
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... JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored. (3) Do not leave the MSEL pins floating. Connect them to V Altera recommends connecting the MSEL pins to GND if your device is only using JTAG configuration. Table 8–4. Configuration Schemes for Cyclone IV GX Devices (EP4CGX30 [only for F484 package], EP4CGX50, EP4CGX75, ...
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... JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored. (3) Do not leave the MSEL pins floating. Connect them to V Altera recommends connecting the MSEL pins to GND if your device is only using JTAG configuration. 1 Smaller Cyclone IV E devices or package options (E144 and F256 packages) do not have the MSEL[3]pin ...
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... Serial data output (DATA) ■ ■ Active-low chip select (nCS) ■ AS data input (ASDI) This four-pin interface connects to Cyclone IV device pins, as shown in Cyclone IV Device Handbook, Volume 1 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices © December 2010 Altera Corporation Configuration Serial in Figure 8–2. ...
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... EPCS device specifications. Cyclone IV devices offer the option to select CLKUSR as the external clock source for DCLK. You can change the clock source option in the Quartus II software in the Configuration tab of the Device and Pin Options dialog box. © December 2010 Altera Corporation V (1) V ...
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... CONF_DONE, DCLK, and DATA[0] pins of each device in the chain are connected together (Figure Cyclone IV Device Handbook, Volume 1 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices timing parameters are identical to the timing parameters for CD2UM Table 8–10 on page 8–35. 8–3). Configuration , CF2CD CF2ST0 CFG © December 2010 Altera Corporation ...
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... Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK. The first Cyclone IV device in the chain is the configuration master and it controls the configuration of the entire chain. Other Altera devices that support PS configuration can also be part of the chain as configuration slaves. ...
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... Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Figure 8–3 on page 8–13. These pins are Figure 8–3 on page Figure 8–4. The first device is the master device Figure 8–4 is that you can have a different .sof for the © December 2010 Altera Corporation Configuration 8–13. ...
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... These pins are dual-purpose I/O pins. The nCSO pin functions as FLASH_nCE pin in AP mode. The ASDO pin functions as DATA[1] pin in AP and FPP modes. (9) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK. © December 2010 Altera Corporation (1) (1) ...
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... MSEL[ ] 8–8, and Table 8–5 on page 8–9. Connect the MSEL pins directly to V Configuration Cyclone IV Slave Device 2 nSTATUS CONF_DONE nCONFIG N.C. (2) nCE nCEO N.C. (2) GND DATA[0] DCLK (3) MSEL[ ] (3) or GND. CCA “Configuration and JTAG Pin I/O © December 2010 Altera Corporation ...
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... Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices Configuration Altera recommends putting a buffer before the DATA and DCLK output from the master device to avoid signal strength and signal integrity issues. The buffer must not significantly change the DATA-to-DCLK relationships or delay them with respect to other AS signals (ASDI and nCS) ...
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... The existing diodes and capacitors are sufficient. Altera has developed the Serial FlashLoader (SFL), a JTAG-based in-system programming solution for Altera serial configuration devices. The SFL is a bridge design for the Cyclone IV device that uses its JTAG interface to access the EPCS JIC (JTAG Indirect Configuration Device Programming) file and then uses the AS interface to program the EPCS device ...
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... AC voltage of 4.1 V. The external diodes and capacitors are required to prevent damage to the Cyclone IV device AS configuration input pins due to possible overshoot when programming the serial configuration device with a download cable. Altera recommends using the Schottky diode, which has a relatively lower forward diode voltage (VF) than the switching and Zener diodes, for effective voltage clamping. ...
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... In production environments, serial configuration devices are programmed using multiple methods. Altera programming hardware or other third-party programming hardware is used to program blank serial configuration devices before they are mounted onto PCBs. Alternatively, you can use an on-board microprocessor to program the serial configuration device in-system by porting the reference C-based SRunner software driver provided by Altera ...
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... MHz and above. However, AP configuration for all these speed grades must be capped at 40 MHz. The advantage of faster speed grades is realized when your design in the Cyclone IV E devices accesses flash memory in user mode. © December 2010 Altera Corporation Numonyx P30 Flash Family (2) ...
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... Cyclone IV Device Handbook, Volume 1 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices © December 2010 Altera Corporation Configuration ...
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... If you use the AP configuration scheme for Cyclone IV E devices, the V banks and 8 must be 3.3, 3.0, 2.5, or 1.8 V. Altera does not recommend using the level shifter between the Numonyx P30 or P33 flash and the Cyclone IV E device in the AP configuration scheme. ...
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... The remaining Cyclone IV E devices are used as configuration slaves. You must connect their MSEL pins to select the FPP configuration scheme. Any other Altera device that supports FPP configuration can also be part of the chain as a configuration slave. The following are the configurations for the DATA[15..0] bus in a multi-device AP configuration: ■ ...
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... LSB of the DATA[7..0]and the remaining slave devices are connected to the MSB of the DATA[15..8]. In the word-wide multi-device AP configuration, the nCEO pin of the master device enables two separate daisy chains of slave devices, allowing both chains to be programmed concurrently, as shown in © December 2010 Altera Corporation 8–8. V CCIO (1) V CCIO (1) V CCIO (2) 10 kΩ ...
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... Cyclone IV E Slave Device or GND. CCA 8–5. Configuration V CCIO (2) nCE nCEO N.C. (3) (4) MSEL[3..0] (4) DQ[7..0] DATA[7..0] DCLK Cyclone IV E Slave Device nCE nCEO N.C. (3) MSEL[3..0] (4) (4) DATA[7..0] DCLK DQ[15..8] Cyclone IV E Slave Device Table 8–5 on Table 8–9. © December 2010 Altera Corporation ...
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... In the AP configuration scheme, multiple masters share the parallel flash. Similar to the AS configuration scheme, the bus control is negotiated by the nCE pin. © December 2010 Altera Corporation Figure 8–8 on page 8–25 Table 8– ...
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... JTAG Pin I/O Requirements” on page “Configuration and JTAG Pin I/O Requirements” on page CCIO Configuration (1) V CCIO V (1) CCIO 10 k 10 k nCEO (2) MSEL[3..0] (3) Cyclone IV E Master Device Table 8–5 on 8–5. 8–5. . © December 2010 Altera Corporation ...
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... Figure 8–11: (1) Altera recommends that M does not exceed 6 inches, as listed in (2) Altera recommends using a balanced star routing. Keep the N length equal and as short as possible to minimize reflection noise from the transmission line. The M length is applicable for this setup. Estimating AP Configuration Time AP configuration time is dominated by the time it takes to transfer data from the parallel flash to Cyclone IV E devices ...
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... Instructions” on page Cyclone IV Device Handbook, Volume 1 Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices AN 478: Using FPGA-Based Parallel Flash Loader Software. Figure 8–12 shows the configuration boot address in the AP 8–56. Configuration Table 8–8 on “JTAG © December 2010 Altera Corporation ...
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... Cyclone IV device. f For more information about the PFL, refer to with the Quartus II 1 Cyclone IV devices do not support enhanced configuration devices for PS configuration. © December 2010 Altera Corporation Bottom Parameter Flash Memory Other data/code Cyclone IV E Default Boot Configuration Address ...
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... DCLK (4) specification of the I/O on the device and the external host. IH 8–8, Table 8–4 on page 8–8, and Table 8–5 on page 8–5. Configuration Cyclone IV Device (3) MSEL[ ] nCEO N.C. (2) must be high CC 8–9. Connect the MSEL pins directly © December 2010 Altera Corporation ...
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... Table 8–3 on page GND. CCA (5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot outlined in Equation 8–1 on page © December 2010 Altera Corporation V (1) V (1) Cyclone IV Device 1 CCIO CCIO 10 k 10 k ...
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... I/O on the device and the external host. IH 8–8, Table 8–4 on page 8–8, and Table 8–5 on page 8–5. Configuration Cyclone IV Slave Device (3) (3) MSEL[ ] CONF_DONE nSTATUS N.C. (2) nCE N.C. (2) nCEO GND DATA[0] (4) nCONFIG DCLK (4) 8–9. Connect the MSEL pins directly © December 2010 Altera Corporation ...