EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 81

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Cyclone IV PLL Hardware Overview
Cyclone IV PLL Hardware Overview
Figure 5–9. Cyclone IV GX PLL Block Diagram
Notes to
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) There are additional 4 pairs of dedicated differential clock inputs in EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices that can only
(3) This is the VCO post
(4) This input port is fed by a pin
(5) For the general purpose PLL and multipurpose PLL counter outputs connectivity to the GCLKs, refer to
(6) Only the CI output counter can drive the TX serial clock.
(7) Only the C2 output counter can drive the TX load enable.
(8) Only the C3 output counter can drive the TX parallel clock.
© December 2010 Altera Corporation
Clock inputs
from pins
GCLK
drive general purpose PLLs and multipurpose PLLs on the left side of the device. CLK[19..16] can access PLL_2, PLL_6, PLL_7, and
PLL_8 while CLK[23..20] can access PLL_1, PLL_5, PLL_6, and PLL_7. For the location of these clock input pins, refer to
on page
PLL or a pin
page
pfdena
(4)
Figure
5–4.
5–12.
4 (2)
-
5–9:
driven dedicated GCLK. An internally generated global signal cannot drive the PLL.
-
inclk0
inclk1
scale counter K.
This section gives a hardware overview of the Cyclone IV PLL.
Figure 5–9
Cyclone IV GX devices.
(MPLLs, GPLL1, and GPLL2 only)
Switchover
-
Clock
Block
driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another
FREF for ppm detect
shows a simplified block diagram of the major components of the PLL of
÷n
clkswitch
clkbad0
clkbad1
activeclock
(Note 1)
PFD
LOCK
circuit
CP
Detector
Range
VCO
lock
Deterministic Latency compensation
(MPLLs, GPLL1, and GPLL2 only)
LF
VCO
8
VCOOVRR
VCOUNDR
no compensation;
source-synchronous;
normal mode
÷2 (3)
ZDB mode
÷ 2, ÷ 4
8
8
÷M
To RX CDR clocks
(MPLLs only)
÷C0
÷C1
÷C2
÷C3
÷C4
Table 5–1 on page 5–2
Cyclone IV Device Handbook, Volume 1
output
mux
PLL
GCLKs (5)
External clock output
TX serial clock (MPLLs,
GPLL1, and GPLL2 only) (6)
TX load enable (MPLLs,
GPLL1, and GPLL2 only) (7)
TX parallel clock (MPLLs ,
GPLL1, and GPLL2only) (8)
GCLK networks
and
Table 5–2 on
Figure 5–3
5–19