EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 400

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

3–10
Figure 3–3. Dynamic Reconfiguration Signals Transition during Offset Cancellation
Notes to
(1) After device power up, the busy signal remains low for the first reconfig_clk cycle.
(2) The busy signal then gets asserted for the second reconfig_clk cycle, when the dynamic reconfiguration controller initiates the offset
(3) The deassertion of the busy signal indicates the successful completion of the offset cancellation process.
Dynamic Reconfiguration Modes
Cyclone IV Device Handbook, Volume 2
cancellation process.
Figure
3–3:
1
reconfig_clk
The gxb_powerdown signal must not be asserted during the offset cancellation
sequence.
Figure 3–3
Functional Simulation of the Offset Cancellation Process
You must connect the ALTGX_RECONFIG instances to the ALTGX instances in your
design for functional simulation. Functional simulation uses a reduced timing model
of the dynamic reconfiguration controller. Therefore, the duration of the offset
cancellation process is 16 reconfig_clk clock cycles for functional simulation only.
The gxb_powerdown signal must not be asserted during the offset cancellation
sequence (for functional simulation and silicon).
When you enable the dynamic reconfiguration feature, you can reconfigure the
following portions of each transceiver channel dynamically, without powering down
the other transceiver channels or the FPGA fabric of the device:
■
■
■
busy
Analog (PMA) controls reconfiguration
Channel reconfiguration
PLL reconfiguration
(1)
shows the timing diagram for a offset cancellation process.
(2)
Chapter 3: Cyclone IV Dynamic Reconfiguration
(3)
© December 2010 Altera Corporation
Dynamic Reconfiguration Modes