EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 193

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
The nSTATUS and CONF_DONE pins on all target devices are connected together with
external pull-up resistors, as shown in
page
device asserts nCEO (after receiving all its configuration data), it releases its
CONF_DONE pin. However, the subsequent devices in the chain keep this shared
CONF_DONE line low until they receive their configuration data. When all target
devices in the chain receive their configuration data and release CONF_DONE, the
pull-up resistor drives a high level on this line and all devices simultaneously enter
initialization mode.
Guidelines for Connecting Parallel Flash to Cyclone IV E Devices for an AP Interface
For single- and multi-device AP configuration, the board trace length and loading
between the supported parallel flash and Cyclone IV E devices must follow the
recommendations listed in
configuration with multiple bus masters.
Table 8–9. Maximum Trace Length and Loading for AP Configuration
Configuring With Multiple Bus Masters
Similar to the AS configuration scheme, the AP configuration scheme supports
multiple bus masters for the parallel flash. For another master to take control of the
AP configuration bus, the master must assert nCONFIG low for at least 500 ns to reset
the master Cyclone IV E device and override the weak 10-k pull-down resistor on
the nCE pin. This resets the master Cyclone IV E device and causes it to tri-state its AP
configuration bus. The other master device then takes control of the AP configuration
bus. After the other master device is done, it releases the AP configuration bus, then
releases the nCE pin, and finally pulses nCONFIG low to restart the configuration.
In the AP configuration scheme, multiple masters share the parallel flash. Similar to
the AS configuration scheme, the bus control is negotiated by the nCE pin.
DCLK
DATA[15..0]
PADD[23..0]
nRESET
Flash_nCE
nOE
nAVD
nWE
I/O
Note to
(1) The AP configuration ignores the WAIT signal from the flash during configuration mode. However, if you are
Cyclone IV E AP Pins
accessing flash during user mode with user logic, you can optionally use the normal I/O to monitor the WAIT signal
from the Numonyx P30 or P33 flash.
8–26. These pins are open-drain bidirectional pins on the devices. When the first
(1)
Table
8–9:
Cyclone IV E Device to Flash Device
Maximum Board Trace Length from
Table
8–9. These recommendations also apply to an AP
(inches)
Figure 8–8 on page 8–25
6
6
6
6
6
6
6
6
6
Cyclone IV Device Handbook, Volume 1
Maximum Board Load (pF)
and
Figure 8–9 on
15
30
30
30
30
30
30
30
30
8–27