EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 147

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EP4CE55F23C7

Manufacturer Part Number
EP4CE55F23C7
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er

Specifications of EP4CE55F23C7

Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Chapter 6: I/O Features in Cyclone IV Devices
Software Overview
Software Overview
© December 2010 Altera Corporation
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f
1
For PCB layout guidelines, refer to
AN 315: Guidelines for Designing High-Speed FPGA
Cyclone IV devices high-speed I/O system interfaces are created in core logic by a
Quartus II software megafunction because they do not have a dedicated circuit for the
SERDES. Cyclone IV devices use the I/O registers and LE registers to improve the
timing performance and support the SERDES. The Quartus II software allows you to
design your high-speed interfaces using ALTLVDS megafunction. This megafunction
implements either a high-speed deserializer receiver or a high-speed serializer
transmitter. There is a list of parameters in the ALTLVDS megafunction that you can
set to customize your SERDES based on your design requirements. The megafunction
is optimized to use Cyclone IV devices resources to create high-speed I/O interfaces
in the most effective manner.
When you use Cyclone IV devices with the ALTLVDS megafunction, the interface
always sends the MSB of your parallel data first.
For more details about designing your high-speed I/O systems interfaces using the
ALTLVDS megafunction, refer to the
Quartus II
Handbook.
AN 224: High-Speed Board Layout Guidelines
ALTLVDS Megafunction User Guide
PCBs.
Cyclone IV Device Handbook, Volume 1
and the
and
6–39

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