EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 325

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Figure 1–46. Transceiver Configurations in Basic Mode with a 10-Bit Wide PMA-to-PCS Interface
© December 2010 Altera Corporation
FPGA Fabric-to-
Transceiver
Interface Width
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner
(Pattern Length)
8B/10B
Encoder/Decoder
Rate Match FIFO
Byte SERDES
Byte Ordering
Data Rate (Gbps)
FPGA Fabric-to-
Transceiver
Interface
Fredquency (MHz)
Disabled Enabled
Disabled
1.5625
156.25
10-Bit
1.25
0.6-
0.6-
125
60-
60-
Disabled
Disabled
Disabled
Manual Alignment
156.25
20-Bit
3.125
In Basic mode, the transceiver supports the following additional options:
■
■
■
■
Low-Latency PCS Operation
When configured in low-latency PCS operation, the following blocks in the
transceiver PCS are bypassed, resulting in a lower latency PCS datapath:
■
■
■
■
0.6-
0.6-
125
30-
(7-Bit, 10-Bit)
2.5
30-
low-latency PCS operation
transmitter in electrical idle
receiver signal detect
receiver spread spectrum clocking
8B/10B encoder and decoder
word aligner
rate match FIFO
byte ordering
Disabled Enabled
Disabled
156.25
1.5625
1.25
8-Bit
0.6-
125
0.6-
60-
60-
Disabled
Enabled
Disabled
156.25
16-Bit
3.125
Applicable for devices in
F324 and smaller packages
0.6-
125
0.6-
30-
30-
2.5
Disabled Enabled
Disabled
156.25
1.5625
10-Bit
1.25
125
0.6-
60-
0.6-
60-
Disabled
Disabled
Disabled
156.25
20-Bit
3.125
125
0.6-
30-
0.6-
30-
2.5
(7-Bit, 10-Bit)
Bit Slip
Disabled Enabled
Disabled
156.25
1.5625
Disabled
8-Bit
1.25
125
0.6-
0.6-
60-
60-
Disabled
Enabled
Basic (10-Bit PMA-PCS Interface Width)
Disabled
156.25
16-Bit
3.125
125
0.6-
0.6-
30-
2.5
30-
Disabled Enabled
Disabled
×1, ×2, ×4
1.5625
156.25
10-Bit
1.25
0.6-
0.6-
125
60-
60-
Disabled
Disabled
Disabled
Applicable for devices in
F484 and larger packages
156.25
20-Bit
3.125
0.6-
0.6-
125
2.5
30-
30-
State Machine (7-Bit, 10-Bit)
Automatic Synchronization
Disabled
Disabled
156.25
1.5625
1.25
8-Bit
125
0.6-
60-
60-
0.6-
Disabled
Disabled
156.25
16-Bit
125
30-
30-
Enabled
3.125
0.6-
0.6-
2.5
Cyclone IV Device Handbook, Volume 2
156.25
Enabled
Enabled
16-Bit
125
30-
30-
Disabled Enabled
Disabled
1.5625
156.25
1.25
8-Bit
125
0.6-
0.6-
60-
60-
Enabled
Disabled
156.25
16-Bit
3.125
125
0.6-
0.6-
30-
2.5
30-
Disabled
Disabled Disabled
1.5625
10-Bit
156.25
1.25
0.6-
0.6-
125
60-
60-
Disabled
Disabled
Disabled
Enabled
Enabled
156.25
3.125
20-Bit
125
0.6-
0.6-
30-
30-
2.5
1–45