EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 317

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Figure 1–39. Transmitter and Receiver Datapath Clocking with Rate Match FIFO in Bonded Channel Configuration
Notes to
(1) Low-speed recovered clock.
(2) High-speed recovered clock.
© December 2010 Altera Corporation
Fabric
FPGA
Figure 1–39
coreclkout
:
/2
Phase
Phase
Phase
Phase
Comp
Comp
Comp
Comp
FIFO
FIFO
FIFO
FIFO
Rx
Rx
Rx
Rx
wr_clk
wr_clk
wr_clk
wr_clk
Tx Phase
Tx Phase
Tx Phase
Tx Phase
Comp
Comp
Comp
Comp
FIFO
FIFO
FIFO
FIFO
rd_clk
rd_clk
rd_clk
rd_clk
Order-
Order-
Order-
Order-
Byte
Byte
Byte
Byte
ing
ing
ing
ing
/2
/2
/2
/2
serializer
serializer
serializer
serializer
Byte
Byte
Byte
Byte
De-
De-
De-
De-
wr_clk
wr_clk
wr_clk
wr_clk
Byte Serializer
Byte Serializer
Byte Serializer
Byte Serializer
/2
/2
/2
/2
Transmitter Channel PCS 3
Transmitter Channel PCS 2
Transmitter Channel PCS 1
Transmitter Channel PCS 0
Receiver Channel PCS 3
Decoder
Receiver Channel PCS 2
Decoder
Receiver Channel PCS 1
Decoder
Receiver Channel PCS 0
Decoder
8B/10B
8B/10B
8B/10B
8B/10B
rd_clk
rd_clk
rd_clk
rd_clk
Match
Match
Match
Match
FIFO
FIFO
FIFO
FIFO
Rate
Rate
Rate
Rate
8B/10B Encoder
8B/10B Encoder
8B/10B Encoder
8B/10B Encoder
Deskew
Deskew
Deskew
Deskew
FIFO
FIFO
FIFO
FIFO
(1)
(1)
(1)
(1)
Aligner
Aligner
Aligner
Aligner
Cyclone IV Device Handbook, Volume 2
Word
Word
Word
Word
In 2 Bonded Channel Configuration
Deserial-
Deserial-
Deserial-
Deserial-
Transmitter Channel PMA 3
Receiver Channel PMA 3
Transmitter Channel PMA 2
Receiver Channel PMA 2
Transmitter Channel PMA 1
Receiver Channel PMA 1
Transmitter Channel PMA 0
Receiver Channel PMA 0
In 4 Bonded Channel Configuration
izer
izer
izer
izer
Serializer
Serializer
Serializer
Serializer
(2)
(2)
(2)
(2)
CDR
CDR
CDR
CDR
low-speed clock
high-speed
clock
high-speed
clock
high-speed
clock
high-speed
clock
CDR clock
CDR clock
CDR clock
CDR clock
1–37