EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 256

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

9–10
Table 9–7. CRC Block Input and Output Ports (Part 2 of 2)
Recovering from CRC Errors
Document Revision History
Table 9–8. Document Revision History
Cyclone IV Device Handbook, Volume 1
.crcerror
(<crcerror
indicator
output>)
.regout
(<registered
output>)
February 2009
November 2009
Date
Port
The system that the Altera FPGA resides in must control device reconfiguration. After
detecting an error on the CRC_ERROR pin, strobing the nCONFIG low directs the
system to perform the reconfiguration at a time when it is safe for the system to
reconfigure the FPGA.
When the data bit is rewritten with the correct value by reconfiguring the device, the
device functions correctly.
While soft errors are uncommon in Altera devices, certain high-reliability applications
might require a design to account for these errors.
Table 9–8
Version
1.1
1.0
Input/Output
Output
Output
lists the revision history for this chapter.
Updated for the Quartus II software version 9.1 SP1 release:
■
■
■
Initial release.
Updated
Updated
Added Cyclone IV E devices in
This signal is the output of the cell that is synchronized to the internal oscillator of
the device (80-MHz internal oscillator) and not to the clk port. It asserts high if
the error block detects that a SRAM bit has flipped and the internal CRC
computation has shown a difference with respect to the pre-computed value. You
must connect this signal either to an output pin or a bidirectional pin. If it is
connected to an output pin, you can only monitor the CRC_ERROR pin (the core
cannot access this output). If the CRC_ERROR signal is used by core logic to read
error detection logic, you must connect this signal to a BIDIR pin. The signal is
fed to the core indirectly by feeding a BIDIR pin that has its output enable port
connected to V
This signal is the output of the error detection shift register synchronized to the
clk port to be read by core logic. It shifts one bit at each cycle, so you should
clock the clk signal 31 cycles to read out the 32 bits of the shift register.
“Configuration Error Detection”
Table
9–6.
CC
(see
Figure 9–3 on page
Table
Changes Made
9–6.
Definition
section.
Chapter 9: SEU Mitigation in Cyclone IV Devices
9–8).
© February 2010 Altera Corporation
Recovering from CRC Errors