EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 146

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

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Design Guidelines
Differential Pad Placement Guidelines
Board Design Considerations
Cyclone IV Device Handbook, Volume 1
1
This section provides guidelines for designing with Cyclone IV devices.
To maintain an acceptable noise level on the V
restrictions on the placement of single-ended I/O pins in relation to differential pads.
For guidelines on placing single-ended pads with respect to differential pads in
Cyclone IV devices, refer to
This section explains how to achieve the optimal performance from a Cyclone IV I/O
interface and ensure first-time success in implementing a functional design with
optimal signal quality. You must consider the critical issues of controlled impedance
of traces and connectors, differential routing, and termination techniques to get the
best performance from Cyclone IV devices.
Use the following general guidelines to improve signal quality:
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Base board designs on controlled differential impedance. Calculate and compare
all parameters, such as trace width, trace thickness, and the distance between two
differential traces.
Maintain equal distance between traces in differential I/O standard pairs as much
as possible. Routing the pair of traces close to each other maximizes the
common-mode rejection ratio (CMRR).
Longer traces have more inductance and capacitance. These traces must be as
short as possible to limit signal integrity issues.
Place termination resistors as close to receiver input pins as possible.
Use surface mount components.
Avoid 90° corners on board traces.
Use high-performance connectors.
Design backplane and card traces so that trace impedance matches the impedance
of the connector and termination.
Keep an equal number of vias for both signal traces.
Create equal trace lengths to avoid skew between signals. Unequal trace lengths
result in misplaced crossing points and decrease system margins as the TCCS
value increases.
Limit vias because they cause discontinuities.
Keep switching transistor-to-transistor logic (TTL) signals away from differential
signals to avoid possible noise coupling.
Do not route TTL clock signals to areas under or above the differential signals.
Analyze system-level signals.
“Pad Placement and DC Guidelines” on page
CCIO
supply, you must observe some
Chapter 6: I/O Features in Cyclone IV Devices
© December 2010 Altera Corporation
Design Guidelines
6–22.