EP1AGX90EF1152I6 Altera, EP1AGX90EF1152I6 Datasheet - Page 48

IC ARRIA GX FPGA 90K 1152FBGA

EP1AGX90EF1152I6

Manufacturer Part Number
EP1AGX90EF1152I6
Description
IC ARRIA GX FPGA 90K 1152FBGA
Manufacturer
Altera
Series
Arria GXr
Datasheet

Specifications of EP1AGX90EF1152I6

Number Of Logic Elements/cells
90220
Number Of Labs/clbs
4511
Total Ram Bits
4477824
Number Of I /o
538
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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2–42
Register Chain
Arria GX Device Handbook, Volume 1
chains are also top- or bottom-half bypassable. This capability allows the shared
arithmetic chain to cascade through half of the ALMs in a LAB while leaving the other
half available for narrower fan-in functionality. Every other LAB column is top-half
bypassable, while the other LAB columns are bottom-half bypassable. For more
information about shared arithmetic chain interconnect, refer to
Interconnect” on page
In addition to the general routing outputs, the ALMs in a LAB have register chain
outputs. Register chain routing allows registers in the same LAB to be cascaded
together. The register chain interconnect allows a LAB to use LUTs for a single
combinational function and the registers to be used for an unrelated shift register
implementation. These resources speed up connections between ALMs while saving
local interconnect resources (refer to
automatically takes advantage of these resources to improve utilization and
performance. For more information about register chain interconnect, refer to
“MultiTrack Interconnect” on page
2–44.
2–44.
Figure
2–38). The Quartus II Compiler
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
“MultiTrack
Adaptive Logic Modules

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