EP2AGX125EF35C5N Altera, EP2AGX125EF35C5N Datasheet - Page 72

• Manufacturer Part Number: EP2AGX125EF35C5N
• Description: IC ARRIA II GX 125K 1152FBG
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX125EF35C5N

• Number Of Logic Elements/cells: 118143
• Number Of Labs/clbs: 4964
• Total Ram Bits: 8121
• Number Of I /o: 452
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2600 - KIT DEV ARRIA II GX FPGA 2AGX125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2598-5; 544-2644; 544-2644; EP2AGX125EF35C5NES; EP2AGX125EF35C5NES

1–64
Table 1–49. Embedded Memory Block Performance Specifications for Arria II GZ Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
MLAB
M9K
Block
M144K
Block
Notes to
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
(2) When you use the error detection CRC feature, there is no degradation in F
Memory
(2)
set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2)
(2)
Table
Single port 64 × 10
Simple dual-port 32 × 20
Simple dual-port 64 × 10
ROM 64 × 10
ROM 32 × 20
Single-port 256 × 36
Simple dual-port 256 × 36
Simple dual-port 256 × 36, with the
read-during-write option set to Old
Data
True dual port 512 × 18
True dual-port 512 × 18, with the
read-during-write option set to Old
Data
ROM 1 Port
ROM 2 Port
Min Pulse Width (clock high time)
Min Pulse Width (clock low time)
Single-port 2K × 72
Simple dual-port 2K × 72
Simple dual-port 2K × 72, with the
read-during-write option set to Old
Data
Simple dual-port 2K × 64 (with ECC)
True dual-port 4K × 36
True dual-port 4K × 36, with the
read-during-write option set to Old
Data
ROM 1 Port
ROM 2 Port
Min Pulse Width (clock high time)
Min Pulse Width (clock low time)
1–48:
Table 1–49
Mode
lists the embedded memory block specifications for Arria II GZ devices.
ALUTs
Resources Used
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TriMatrix
Memory
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MAX
.
500
500
500
500
500
540
490
340
430
335
540
540
800
625
440
435
240
300
375
230
500
465
755
625
C3
Chapter 1: Device Datasheet for Arria II Devices
500
500
500
500
500
540
490
340
430
335
540
540
800
625
400
375
225
295
350
225
450
425
860
690
Performance
I3
December 2010 Altera Corporation
(Note 1)
450
450
450
450
450
475
420
300
370
290
475
475
850
690
380
385
205
255
330
205
435
400
860
690
C4
Switching Characteristics
450
450
450
450
450
475
420
300
370
290
475
475
850
690
350
325
200
250
310
200
420
400
950
690
I4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps
ps
ps
ps