EP2AGX125EF35C5N Altera, EP2AGX125EF35C5N Datasheet - Page 82
EP2AGX125EF35C5N
Manufacturer Part Number
EP2AGX125EF35C5N
Description
IC ARRIA II GX 125K 1152FBG
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX125EF35C5N
Number Of Logic Elements/cells
118143
Number Of Labs/clbs
4964
Total Ram Bits
8121
Number Of I /o
452
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2600 - KIT DEV ARRIA II GX FPGA 2AGX125
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2598-5
544-2644
544-2644
EP2AGX125EF35C5NES
EP2AGX125EF35C5NES
544-2644
544-2644
EP2AGX125EF35C5NES
EP2AGX125EF35C5NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX125EF35C5N
Manufacturer:
TOSHIBA
Quantity:
12 000
Company:
Part Number:
EP2AGX125EF35C5N
Manufacturer:
ALTERA21
Quantity:
144
1–74
Table 1–58. DLL Frequency Range Specifications for Arria II GZ Devices (Part 2 of 2)
Table 1–61. Memory Output Clock Jitter Specification for Arria II GX Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Note to
(1) Low indicates a 6-bit DQS delay setting; high indicates a 5-bit DQS delay setting.
Clock period jitter
Cycle-to-cycle period
jitter
Frequency Mode
Parameter
Table
7
1–58:
Table 1–59
Table 1–59. DQS Phase Offset Delay Per Setting for Arria II GX Devices
Table 1–60
Table 1–60. DQS Phase Shift Error Specification for DLL-Delayed Clock (t
Devices
Table 1–61
Notes to
(1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes
(2) The typical value equals the average of the minimum and maximum values.
(3) The delay settings are linear.
Note to
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
Network
470-630
Number of DQS Delay Buffer
Global
Global
Clock
4 to 5.
buffers in a 3 speed grade is ± 78 ps or ± 39 ps.
Frequency Range (MHz)
–3
Table
Table
(Note 1)
Speed Grade
lists the DQS phase offset delay per stage for Arria II GX devices.
lists the DQS phase shift error for Arria II GZ devices.
lists the memory output clock jitter specifications for Arria II GX devices.
I3, C5, I5
1–60:
1–59:
C4
C6
Symbol
1
2
3
4
t
t
JIT(per)
JIT(cc)
470-590
–4
-100
-200
Min
–4
Max
100
200
Available Phase Shift
60°, 120°, 180°, 240°
Min
7.0
7.0
8.5
112
–3
28
56
84
-125
-250
Min
(Note
Chapter 1: Device Datasheet for Arria II Devices
–5
Max
1), (2),
125
250
Max
13.0
15.0
18.0
December 2010 Altera Corporation
120
–4
30
60
90
Buffer Mode
(3)
DQS Delay
-125
-250
Min
(Note
DQS_PSERR
(Part 1 of 2)
High
(1)
Switching Characteristics
–6
1), (2),
) for Arria II GZ
Max
125
250
Unit
Number of
ps
ps
ps
(3)
Chains
Unit
Delay
ps
ps
ps
ps
6
Unit
ps
ps